convolution.v

来自「本例是关于卷积码的一个简单算法」· Verilog 代码 · 共 63 行

module convolution
(
	clk,
	reset,
	code_in,
	code_out,
	valid_in,
	valid_out
	//next_state
);

input clk;
input reset;
input code_in;
input valid_in;
output[2:0] code_out;
output valid_out;
//output [2:0] next_state;

reg valid_out=0;
reg [2:0] code_out=0;
reg [2:0] next_state=0;

always@(posedge clk) 
begin
if(reset) 
	begin
		code_out<=0;
		next_state<=0;
		valid_out<=0;
	end
else if(valid_in)
	begin
		next_state[0]<=next_state[1];
		next_state[1]<=next_state[2];
		next_state[2]<=code_in;
		code_out[2]<=next_state[2];
		code_out[1]<=next_state[2]+next_state[1];
		code_out[0]<=next_state[2]+next_state[0];
		valid_out<=1;
	end
	else
		begin
			if(valid_out)
				begin
					valid_out<=0;
				end
		end
end
endmodule