prev_cmp_counter16.qmsg

利用VHDL编写的一个简单的16位计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 01 16:03:28 2009 " "Info: Processing started: Wed Apr 01 16:03:28 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counter16 -c counter16 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off counter16 -c counter16" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter16.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter16-behav " "Info: Found design unit 1: counter16-behav" {  } { { "counter16.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/jian/counter16.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter16 " "Info: Found entity 1: counter16" {  } { { "counter16.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/jian/counter16.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VHDL_WRONG_SIGNAL_ASSIGN" "Qtemp counter16.vhd(18) " "Error (10526): VHDL Signal Assignment Statement error at counter16.vhd(18): Signal Assignment Statement must use <= to assign value to signal \"Qtemp\"" {  } { { "counter16.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/jian/counter16.vhd" 18 0 0 } }  } 0 10526 "VHDL Signal Assignment Statement error at %2!s!: Signal Assignment Statement must use <= to assign value to signal \"%1!s!\"" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "172 " "Error: Peak virtual memory: 172 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Wed Apr 01 16:03:30 2009 " "Error: Processing ended: Wed Apr 01 16:03:30 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Error: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}