counter16.hier_info

利用VHDL编写的一个简单的16位计数器

|counter16
clr => ~NO_FANOUT~
fin => ~NO_FANOUT~
start => ~NO_FANOUT~
Q[0] <= <GND>
Q[1] <= <GND>
Q[2] <= <GND>
Q[3] <= <GND>
Q[4] <= <GND>
Q[5] <= <GND>
Q[6] <= <GND>
Q[7] <= <GND>
Q[8] <= <GND>
Q[9] <= <GND>
Q[10] <= <GND>
Q[11] <= <GND>
Q[12] <= <GND>
Q[13] <= <GND>
Q[14] <= <GND>
Q[15] <= <GND>