counter16.map.rpt

利用VHDL编写的一个简单的16位计数器

; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                 ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                    ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------+
; counter16.vhd                    ; yes             ; User VHDL File  ; C:/Documents and Settings/Administrator/桌面/jian/counter16.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
;                                             ;       ;
; Total combinational functions               ; 0     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 0     ;
;     -- <=2 input functions                  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 0     ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
;     -- Dedicated logic registers            ; 0     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 19    ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |counter16                 ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 19   ; 0            ; |counter16          ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Wed Apr 01 16:04:10 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off counter16 -c counter16
Info: Found 2 design units, including 1 entities, in source file counter16.vhd
    Info: Found design unit 1: counter16-behav
    Info: Found entity 1: counter16
Info: Elaborating entity "counter16" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at counter16.vhd(24): signal "Qtemp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10873): Using initial value X (don't care) for net "Qtemp[15]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[14]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[13]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[12]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[11]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[10]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[9]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[8]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[7]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[6]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[5]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[4]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[3]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[2]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[1]" at counter16.vhd(14)
Warning (10873): Using initial value X (don't care) for net "Qtemp[0]" at counter16.vhd(14)
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "Q[0]" is stuck at GND
    Warning (13410): Pin "Q[1]" is stuck at GND
    Warning (13410): Pin "Q[2]" is stuck at GND
    Warning (13410): Pin "Q[3]" is stuck at GND
    Warning (13410): Pin "Q[4]" is stuck at GND
    Warning (13410): Pin "Q[5]" is stuck at GND
    Warning (13410): Pin "Q[6]" is stuck at GND
    Warning (13410): Pin "Q[7]" is stuck at GND
    Warning (13410): Pin "Q[8]" is stuck at GND
    Warning (13410): Pin "Q[9]" is stuck at GND
    Warning (13410): Pin "Q[10]" is stuck at GND
    Warning (13410): Pin "Q[11]" is stuck at GND
    Warning (13410): Pin "Q[12]" is stuck at GND
    Warning (13410): Pin "Q[13]" is stuck at GND
    Warning (13410): Pin "Q[14]" is stuck at GND
    Warning (13410): Pin "Q[15]" is stuck at GND
Warning: Design contains 3 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "clr"
    Warning (15610): No output dependent on input pin "fin"
    Warning (15610): No output dependent on input pin "start"
Info: Implemented 19 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 16 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 38 warnings
    Info: Peak virtual memory: 174 megabytes
    Info: Processing ended: Wed Apr 01 16:04:12 2009
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02