buffer422.tan.summary

一个同步422接口控制器的verilog源程序。

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.912 ns
From           : rst
To             : buff_control:inst|data
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.519 ns
From           : buff_control:inst|active
To             : clk_out
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -5.168 ns
From           : clk_in
To             : buff_control:inst|clk_reg
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : 1.169 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : 88.25 MHz ( period = 11.331 ns )
From           : lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dffe9a[9]
To             : lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a6~porta_address_reg11
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : -2.609 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : buff_control:inst|data
To             : lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 17

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 17

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