dcfifo_oi91.tdf

一个同步422接口控制器的verilog源程序。

--dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="TRUE" DEVICE_FAMILY="Cyclone" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=128 LPM_SHOWAHEAD="OFF" LPM_WIDTH=1 LPM_WIDTHU=7 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdreq rdusedw wrclk wrreq CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 6.0 cbx_a_gray2bin 2006:02:28:17:43:38:SJ cbx_a_graycounter 2006:03:13:11:03:08:SJ cbx_altdpram 2006:01:09:10:52:42:SJ cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_dcfifo 2006:03:30:14:19:28:SJ cbx_fifo_common 2006:01:09:11:23:34:SJ cbx_flex10ke 2006:01:09:11:13:48:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_scfifo 2006:01:09:11:24:10:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION alt_sync_fifo_bdm (aclr, data[0..0], rdclk, rdreq, wrclk, wrreq)
RETURNS ( q[0..0], rdempty, rdfull, rdusedw[6..0], wrempty, wrfull, wrusedw[6..0]);

--synthesis_resources = lut 82 M4K 1 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=d101";

SUBDESIGN dcfifo_oi91
( 
	aclr	:	input;
	data[0..0]	:	input;
	q[0..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdfull	:	output;
	rdreq	:	input;
	rdusedw[6..0]	:	output;
	wrclk	:	input;
	wrempty	:	output;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[6..0]	:	output;
) 
VARIABLE 
	sync_fifo : alt_sync_fifo_bdm;

BEGIN 
	sync_fifo.aclr = aclr;
	sync_fifo.data[] = data[];
	sync_fifo.rdclk = rdclk;
	sync_fifo.rdreq = rdreq;
	sync_fifo.wrclk = wrclk;
	sync_fifo.wrreq = wrreq;
	q[] = sync_fifo.q[];
	rdempty = sync_fifo.rdempty;
	rdfull = sync_fifo.rdfull;
	rdusedw[] = sync_fifo.rdusedw[];
	wrempty = sync_fifo.wrempty;
	wrfull = sync_fifo.wrfull;
	wrusedw[] = sync_fifo.wrusedw[];
END;
--VALID FILE