buffer422.hier_info

一个同步422接口控制器的verilog源程序。

clocken1 => address_reg_b[3].ENA
clocken1 => address_reg_b[2].ENA
clocken1 => address_reg_b[1].ENA
clocken1 => address_reg_b[0].ENA
data_a[0] => ram_block15a0.PORTADATAIN
data_a[0] => ram_block15a1.PORTADATAIN
data_a[0] => ram_block15a2.PORTADATAIN
data_a[0] => ram_block15a3.PORTADATAIN
data_a[0] => ram_block15a4.PORTADATAIN
data_a[0] => ram_block15a5.PORTADATAIN
data_a[0] => ram_block15a6.PORTADATAIN
data_a[0] => ram_block15a7.PORTADATAIN
data_a[0] => ram_block15a8.PORTADATAIN
data_a[0] => ram_block15a9.PORTADATAIN
data_a[0] => ram_block15a10.PORTADATAIN
data_a[0] => ram_block15a11.PORTADATAIN
data_a[0] => ram_block15a12.PORTADATAIN
data_a[0] => ram_block15a13.PORTADATAIN
data_a[0] => ram_block15a14.PORTADATAIN
data_a[0] => ram_block15a15.PORTADATAIN
data_a[0] => ram_block15a16.PORTADATAIN
data_a[0] => ram_block15a17.PORTADATAIN
data_a[0] => ram_block15a18.PORTADATAIN
data_a[0] => ram_block15a19.PORTADATAIN
data_a[0] => ram_block15a20.PORTADATAIN
data_a[0] => ram_block15a21.PORTADATAIN
data_a[0] => ram_block15a22.PORTADATAIN
data_a[0] => ram_block15a23.PORTADATAIN
data_a[0] => ram_block15a24.PORTADATAIN
data_a[0] => ram_block15a25.PORTADATAIN
data_a[0] => ram_block15a26.PORTADATAIN
data_a[0] => ram_block15a27.PORTADATAIN
data_a[0] => ram_block15a28.PORTADATAIN
data_a[0] => ram_block15a29.PORTADATAIN
data_a[0] => ram_block15a30.PORTADATAIN
data_a[0] => ram_block15a31.PORTADATAIN
q_b[0] <= mux_6o7:mux17.result[0]
wren_a => decode_tt6:decode16.enable


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|decode_tt6:decode16
data[0] => w_anode499w[1].IN1
data[0] => w_anode519w[1].IN1
data[0] => w_anode539w[1].IN1
data[0] => w_anode559w[1].IN1
data[0] => w_anode591w[1].IN1
data[0] => w_anode611w[1].IN1
data[0] => w_anode631w[1].IN1
data[0] => w_anode651w[1].IN1
data[0] => w_anode682w[1].IN1
data[0] => w_anode702w[1].IN1
data[0] => w_anode722w[1].IN1
data[0] => w_anode742w[1].IN1
data[0] => w_anode773w[1].IN1
data[0] => w_anode793w[1].IN1
data[0] => w_anode813w[1].IN1
data[0] => w_anode833w[1].IN1
data[1] => w_anode509w[2].IN1
data[1] => w_anode519w[2].IN1
data[1] => w_anode549w[2].IN1
data[1] => w_anode559w[2].IN1
data[1] => w_anode601w[2].IN1
data[1] => w_anode611w[2].IN1
data[1] => w_anode641w[2].IN1
data[1] => w_anode651w[2].IN1
data[1] => w_anode692w[2].IN1
data[1] => w_anode702w[2].IN1
data[1] => w_anode732w[2].IN1
data[1] => w_anode742w[2].IN1
data[1] => w_anode783w[2].IN1
data[1] => w_anode793w[2].IN1
data[1] => w_anode823w[2].IN1
data[1] => w_anode833w[2].IN1
data[2] => w_anode529w[3].IN1
data[2] => w_anode539w[3].IN1
data[2] => w_anode549w[3].IN1
data[2] => w_anode559w[3].IN1
data[2] => w_anode621w[3].IN1
data[2] => w_anode631w[3].IN1
data[2] => w_anode641w[3].IN1
data[2] => w_anode651w[3].IN1
data[2] => w_anode712w[3].IN1
data[2] => w_anode722w[3].IN1
data[2] => w_anode732w[3].IN1
data[2] => w_anode742w[3].IN1
data[2] => w_anode803w[3].IN1
data[2] => w_anode813w[3].IN1
data[2] => w_anode823w[3].IN1
data[2] => w_anode833w[3].IN1
data[3] => w_anode571w[1].IN1
data[3] => w_anode753w[1].IN1
data[4] => w_anode662w[2].IN1
data[4] => w_anode753w[2].IN1
enable => w_anode469w[1].IN0
enable => w_anode571w[1].IN0
enable => w_anode662w[1].IN0
enable => w_anode753w[1].IN0
eq[0] <= w_anode482w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode499w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode509w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode519w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[4] <= w_anode529w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[5] <= w_anode539w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[6] <= w_anode549w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[7] <= w_anode559w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[8] <= w_anode580w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[9] <= w_anode591w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[10] <= w_anode601w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[11] <= w_anode611w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[12] <= w_anode621w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[13] <= w_anode631w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[14] <= w_anode641w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[15] <= w_anode651w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[16] <= w_anode671w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[17] <= w_anode682w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[18] <= w_anode692w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[19] <= w_anode702w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[20] <= w_anode712w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[21] <= w_anode722w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[22] <= w_anode732w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[23] <= w_anode742w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[24] <= w_anode762w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[25] <= w_anode773w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[26] <= w_anode783w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[27] <= w_anode793w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[28] <= w_anode803w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[29] <= w_anode813w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[30] <= w_anode823w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[31] <= w_anode833w[3].DB_MAX_OUTPUT_PORT_TYPE


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|decode_tt6:rden_decode
data[0] => w_anode499w[1].IN1
data[0] => w_anode519w[1].IN1
data[0] => w_anode539w[1].IN1
data[0] => w_anode559w[1].IN1
data[0] => w_anode591w[1].IN1
data[0] => w_anode611w[1].IN1
data[0] => w_anode631w[1].IN1
data[0] => w_anode651w[1].IN1
data[0] => w_anode682w[1].IN1
data[0] => w_anode702w[1].IN1
data[0] => w_anode722w[1].IN1
data[0] => w_anode742w[1].IN1
data[0] => w_anode773w[1].IN1
data[0] => w_anode793w[1].IN1
data[0] => w_anode813w[1].IN1
data[0] => w_anode833w[1].IN1
data[1] => w_anode509w[2].IN1
data[1] => w_anode519w[2].IN1
data[1] => w_anode549w[2].IN1
data[1] => w_anode559w[2].IN1
data[1] => w_anode601w[2].IN1
data[1] => w_anode611w[2].IN1
data[1] => w_anode641w[2].IN1
data[1] => w_anode651w[2].IN1
data[1] => w_anode692w[2].IN1
data[1] => w_anode702w[2].IN1
data[1] => w_anode732w[2].IN1
data[1] => w_anode742w[2].IN1
data[1] => w_anode783w[2].IN1
data[1] => w_anode793w[2].IN1
data[1] => w_anode823w[2].IN1
data[1] => w_anode833w[2].IN1
data[2] => w_anode529w[3].IN1
data[2] => w_anode539w[3].IN1
data[2] => w_anode549w[3].IN1
data[2] => w_anode559w[3].IN1
data[2] => w_anode621w[3].IN1
data[2] => w_anode631w[3].IN1
data[2] => w_anode641w[3].IN1
data[2] => w_anode651w[3].IN1
data[2] => w_anode712w[3].IN1
data[2] => w_anode722w[3].IN1
data[2] => w_anode732w[3].IN1
data[2] => w_anode742w[3].IN1
data[2] => w_anode803w[3].IN1
data[2] => w_anode813w[3].IN1
data[2] => w_anode823w[3].IN1
data[2] => w_anode833w[3].IN1
data[3] => w_anode571w[1].IN1
data[3] => w_anode753w[1].IN1
data[4] => w_anode662w[2].IN1
data[4] => w_anode753w[2].IN1
enable => w_anode469w[1].IN0
enable => w_anode571w[1].IN0
enable => w_anode662w[1].IN0
enable => w_anode753w[1].IN0
eq[0] <= w_anode482w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode499w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode509w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode519w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[4] <= w_anode529w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[5] <= w_anode539w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[6] <= w_anode549w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[7] <= w_anode559w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[8] <= w_anode580w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[9] <= w_anode591w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[10] <= w_anode601w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[11] <= w_anode611w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[12] <= w_anode621w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[13] <= w_anode631w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[14] <= w_anode641w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[15] <= w_anode651w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[16] <= w_anode671w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[17] <= w_anode682w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[18] <= w_anode692w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[19] <= w_anode702w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[20] <= w_anode712w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[21] <= w_anode722w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[22] <= w_anode732w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[23] <= w_anode742w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[24] <= w_anode762w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[25] <= w_anode773w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[26] <= w_anode783w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[27] <= w_anode793w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[28] <= w_anode803w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[29] <= w_anode813w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[30] <= w_anode823w[3].DB_MAX_OUTPUT_PORT_TYPE
eq[31] <= w_anode833w[3].DB_MAX_OUTPUT_PORT_TYPE


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|mux_6o7:mux17
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_bg8:add_sub2
cout <= add_sub_cella[16].DB_MAX_OUTPUT_PORT_TYPE
datab[0] => datab_node[0].IN0
datab[1] => datab_node[1].IN0
datab[2] => datab_node[2].IN0
datab[3] => datab_node[3].IN0
datab[4] => datab_node[4].IN0
datab[5] => datab_node[5].IN0
datab[6] => datab_node[6].IN0
datab[7] => datab_node[7].IN0
datab[8] => datab_node[8].IN0
datab[9] => datab_node[9].IN0
datab[10] => datab_node[10].IN0
datab[11] => datab_node[11].IN0
datab[12] => datab_node[12].IN0
datab[13] => datab_node[13].IN0
datab[14] => datab_node[14].IN0
datab[15] => datab_node[15].IN0
datab[16] => datab_node[16].IN0
result[0] <= add_sub_cella[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= add_sub_cella[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= add_sub_cella[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= add_sub_cella[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= add_sub_cella[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= add_sub_cella[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= add_sub_cella[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= add_sub_cella[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= add_sub_cella[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= add_sub_cella[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= add_sub_cella[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= add_sub_cella[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= add_sub_cella[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= add_sub_cella[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= add_sub_cella[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= add_sub_cella[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= add_sub_cella[16].DB_MAX_OUTPUT_PORT_TYPE


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_h18:add_sub3
datab[0] => datab_node[0].IN0
datab[1] => datab_node[1].IN0
datab[2] => datab_node[2].IN0
datab[3] => datab_node[3].IN0
datab[4] => datab_node[4].IN0
datab[5] => datab_node[5].IN0
datab[6] => datab_node[6].IN0
datab[7] => datab_node[7].IN0
datab[8] => datab_node[8].IN0
datab[9] => datab_node[9].IN0
datab[10] => datab_node[10].IN0
datab[11] => datab_node[11].IN0
datab[12] => datab_node[12].IN0
datab[13] => datab_node[13].IN0
datab[14] => datab_node[14].IN0
datab[15] => datab_node[15].IN0
datab[16] => datab_node[16].IN0
datab[17] => datab_node[17].IN0
result[0] <= add_sub_cella[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= add_sub_cella[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= add_sub_cella[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= add_sub_cella[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= add_sub_cella[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= add_sub_cella[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= add_sub_cella[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= add_sub_cella[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= add_sub_cella[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= add_sub_cella[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= add_sub_cella[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= add_sub_cella[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= add_sub_cella[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= add_sub_cella[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= add_sub_cella[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= add_sub_cella[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= add_sub_cella[16].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= add_sub_cella[17].DB_MAX_OUTPUT_PORT_TYPE


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|cntr_q08:cntr1
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
aclr => counter_cella7.ACLR
aclr => counter_cella8.ACLR
aclr => counter_cella9.ACLR
aclr => counter_cella10.ACLR
aclr => counter_cella11.ACLR
aclr => counter_cella12.ACLR
aclr => counter_cella13.ACLR
aclr => counter_cella14.ACLR
aclr => counter_cella15.ACLR
aclr => counter_cella16.ACLR
aclr => counter_cella17.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
c