buffer422.hier_info

一个同步422接口控制器的verilog源程序。

address_b[4] => ram_block15a1.PORTBADDR4
address_b[4] => ram_block15a2.PORTBADDR4
address_b[4] => ram_block15a3.PORTBADDR4
address_b[4] => ram_block15a4.PORTBADDR4
address_b[4] => ram_block15a5.PORTBADDR4
address_b[4] => ram_block15a6.PORTBADDR4
address_b[4] => ram_block15a7.PORTBADDR4
address_b[4] => ram_block15a8.PORTBADDR4
address_b[4] => ram_block15a9.PORTBADDR4
address_b[4] => ram_block15a10.PORTBADDR4
address_b[4] => ram_block15a11.PORTBADDR4
address_b[4] => ram_block15a12.PORTBADDR4
address_b[4] => ram_block15a13.PORTBADDR4
address_b[4] => ram_block15a14.PORTBADDR4
address_b[4] => ram_block15a15.PORTBADDR4
address_b[4] => ram_block15a16.PORTBADDR4
address_b[4] => ram_block15a17.PORTBADDR4
address_b[4] => ram_block15a18.PORTBADDR4
address_b[4] => ram_block15a19.PORTBADDR4
address_b[4] => ram_block15a20.PORTBADDR4
address_b[4] => ram_block15a21.PORTBADDR4
address_b[4] => ram_block15a22.PORTBADDR4
address_b[4] => ram_block15a23.PORTBADDR4
address_b[4] => ram_block15a24.PORTBADDR4
address_b[4] => ram_block15a25.PORTBADDR4
address_b[4] => ram_block15a26.PORTBADDR4
address_b[4] => ram_block15a27.PORTBADDR4
address_b[4] => ram_block15a28.PORTBADDR4
address_b[4] => ram_block15a29.PORTBADDR4
address_b[4] => ram_block15a30.PORTBADDR4
address_b[4] => ram_block15a31.PORTBADDR4
address_b[5] => ram_block15a0.PORTBADDR5
address_b[5] => ram_block15a1.PORTBADDR5
address_b[5] => ram_block15a2.PORTBADDR5
address_b[5] => ram_block15a3.PORTBADDR5
address_b[5] => ram_block15a4.PORTBADDR5
address_b[5] => ram_block15a5.PORTBADDR5
address_b[5] => ram_block15a6.PORTBADDR5
address_b[5] => ram_block15a7.PORTBADDR5
address_b[5] => ram_block15a8.PORTBADDR5
address_b[5] => ram_block15a9.PORTBADDR5
address_b[5] => ram_block15a10.PORTBADDR5
address_b[5] => ram_block15a11.PORTBADDR5
address_b[5] => ram_block15a12.PORTBADDR5
address_b[5] => ram_block15a13.PORTBADDR5
address_b[5] => ram_block15a14.PORTBADDR5
address_b[5] => ram_block15a15.PORTBADDR5
address_b[5] => ram_block15a16.PORTBADDR5
address_b[5] => ram_block15a17.PORTBADDR5
address_b[5] => ram_block15a18.PORTBADDR5
address_b[5] => ram_block15a19.PORTBADDR5
address_b[5] => ram_block15a20.PORTBADDR5
address_b[5] => ram_block15a21.PORTBADDR5
address_b[5] => ram_block15a22.PORTBADDR5
address_b[5] => ram_block15a23.PORTBADDR5
address_b[5] => ram_block15a24.PORTBADDR5
address_b[5] => ram_block15a25.PORTBADDR5
address_b[5] => ram_block15a26.PORTBADDR5
address_b[5] => ram_block15a27.PORTBADDR5
address_b[5] => ram_block15a28.PORTBADDR5
address_b[5] => ram_block15a29.PORTBADDR5
address_b[5] => ram_block15a30.PORTBADDR5
address_b[5] => ram_block15a31.PORTBADDR5
address_b[6] => ram_block15a0.PORTBADDR6
address_b[6] => ram_block15a1.PORTBADDR6
address_b[6] => ram_block15a2.PORTBADDR6
address_b[6] => ram_block15a3.PORTBADDR6
address_b[6] => ram_block15a4.PORTBADDR6
address_b[6] => ram_block15a5.PORTBADDR6
address_b[6] => ram_block15a6.PORTBADDR6
address_b[6] => ram_block15a7.PORTBADDR6
address_b[6] => ram_block15a8.PORTBADDR6
address_b[6] => ram_block15a9.PORTBADDR6
address_b[6] => ram_block15a10.PORTBADDR6
address_b[6] => ram_block15a11.PORTBADDR6
address_b[6] => ram_block15a12.PORTBADDR6
address_b[6] => ram_block15a13.PORTBADDR6
address_b[6] => ram_block15a14.PORTBADDR6
address_b[6] => ram_block15a15.PORTBADDR6
address_b[6] => ram_block15a16.PORTBADDR6
address_b[6] => ram_block15a17.PORTBADDR6
address_b[6] => ram_block15a18.PORTBADDR6
address_b[6] => ram_block15a19.PORTBADDR6
address_b[6] => ram_block15a20.PORTBADDR6
address_b[6] => ram_block15a21.PORTBADDR6
address_b[6] => ram_block15a22.PORTBADDR6
address_b[6] => ram_block15a23.PORTBADDR6
address_b[6] => ram_block15a24.PORTBADDR6
address_b[6] => ram_block15a25.PORTBADDR6
address_b[6] => ram_block15a26.PORTBADDR6
address_b[6] => ram_block15a27.PORTBADDR6
address_b[6] => ram_block15a28.PORTBADDR6
address_b[6] => ram_block15a29.PORTBADDR6
address_b[6] => ram_block15a30.PORTBADDR6
address_b[6] => ram_block15a31.PORTBADDR6
address_b[7] => ram_block15a0.PORTBADDR7
address_b[7] => ram_block15a1.PORTBADDR7
address_b[7] => ram_block15a2.PORTBADDR7
address_b[7] => ram_block15a3.PORTBADDR7
address_b[7] => ram_block15a4.PORTBADDR7
address_b[7] => ram_block15a5.PORTBADDR7
address_b[7] => ram_block15a6.PORTBADDR7
address_b[7] => ram_block15a7.PORTBADDR7
address_b[7] => ram_block15a8.PORTBADDR7
address_b[7] => ram_block15a9.PORTBADDR7
address_b[7] => ram_block15a10.PORTBADDR7
address_b[7] => ram_block15a11.PORTBADDR7
address_b[7] => ram_block15a12.PORTBADDR7
address_b[7] => ram_block15a13.PORTBADDR7
address_b[7] => ram_block15a14.PORTBADDR7
address_b[7] => ram_block15a15.PORTBADDR7
address_b[7] => ram_block15a16.PORTBADDR7
address_b[7] => ram_block15a17.PORTBADDR7
address_b[7] => ram_block15a18.PORTBADDR7
address_b[7] => ram_block15a19.PORTBADDR7
address_b[7] => ram_block15a20.PORTBADDR7
address_b[7] => ram_block15a21.PORTBADDR7
address_b[7] => ram_block15a22.PORTBADDR7
address_b[7] => ram_block15a23.PORTBADDR7
address_b[7] => ram_block15a24.PORTBADDR7
address_b[7] => ram_block15a25.PORTBADDR7
address_b[7] => ram_block15a26.PORTBADDR7
address_b[7] => ram_block15a27.PORTBADDR7
address_b[7] => ram_block15a28.PORTBADDR7
address_b[7] => ram_block15a29.PORTBADDR7
address_b[7] => ram_block15a30.PORTBADDR7
address_b[7] => ram_block15a31.PORTBADDR7
address_b[8] => ram_block15a0.PORTBADDR8
address_b[8] => ram_block15a1.PORTBADDR8
address_b[8] => ram_block15a2.PORTBADDR8
address_b[8] => ram_block15a3.PORTBADDR8
address_b[8] => ram_block15a4.PORTBADDR8
address_b[8] => ram_block15a5.PORTBADDR8
address_b[8] => ram_block15a6.PORTBADDR8
address_b[8] => ram_block15a7.PORTBADDR8
address_b[8] => ram_block15a8.PORTBADDR8
address_b[8] => ram_block15a9.PORTBADDR8
address_b[8] => ram_block15a10.PORTBADDR8
address_b[8] => ram_block15a11.PORTBADDR8
address_b[8] => ram_block15a12.PORTBADDR8
address_b[8] => ram_block15a13.PORTBADDR8
address_b[8] => ram_block15a14.PORTBADDR8
address_b[8] => ram_block15a15.PORTBADDR8
address_b[8] => ram_block15a16.PORTBADDR8
address_b[8] => ram_block15a17.PORTBADDR8
address_b[8] => ram_block15a18.PORTBADDR8
address_b[8] => ram_block15a19.PORTBADDR8
address_b[8] => ram_block15a20.PORTBADDR8
address_b[8] => ram_block15a21.PORTBADDR8
address_b[8] => ram_block15a22.PORTBADDR8
address_b[8] => ram_block15a23.PORTBADDR8
address_b[8] => ram_block15a24.PORTBADDR8
address_b[8] => ram_block15a25.PORTBADDR8
address_b[8] => ram_block15a26.PORTBADDR8
address_b[8] => ram_block15a27.PORTBADDR8
address_b[8] => ram_block15a28.PORTBADDR8
address_b[8] => ram_block15a29.PORTBADDR8
address_b[8] => ram_block15a30.PORTBADDR8
address_b[8] => ram_block15a31.PORTBADDR8
address_b[9] => ram_block15a0.PORTBADDR9
address_b[9] => ram_block15a1.PORTBADDR9
address_b[9] => ram_block15a2.PORTBADDR9
address_b[9] => ram_block15a3.PORTBADDR9
address_b[9] => ram_block15a4.PORTBADDR9
address_b[9] => ram_block15a5.PORTBADDR9
address_b[9] => ram_block15a6.PORTBADDR9
address_b[9] => ram_block15a7.PORTBADDR9
address_b[9] => ram_block15a8.PORTBADDR9
address_b[9] => ram_block15a9.PORTBADDR9
address_b[9] => ram_block15a10.PORTBADDR9
address_b[9] => ram_block15a11.PORTBADDR9
address_b[9] => ram_block15a12.PORTBADDR9
address_b[9] => ram_block15a13.PORTBADDR9
address_b[9] => ram_block15a14.PORTBADDR9
address_b[9] => ram_block15a15.PORTBADDR9
address_b[9] => ram_block15a16.PORTBADDR9
address_b[9] => ram_block15a17.PORTBADDR9
address_b[9] => ram_block15a18.PORTBADDR9
address_b[9] => ram_block15a19.PORTBADDR9
address_b[9] => ram_block15a20.PORTBADDR9
address_b[9] => ram_block15a21.PORTBADDR9
address_b[9] => ram_block15a22.PORTBADDR9
address_b[9] => ram_block15a23.PORTBADDR9
address_b[9] => ram_block15a24.PORTBADDR9
address_b[9] => ram_block15a25.PORTBADDR9
address_b[9] => ram_block15a26.PORTBADDR9
address_b[9] => ram_block15a27.PORTBADDR9
address_b[9] => ram_block15a28.PORTBADDR9
address_b[9] => ram_block15a29.PORTBADDR9
address_b[9] => ram_block15a30.PORTBADDR9
address_b[9] => ram_block15a31.PORTBADDR9
address_b[10] => ram_block15a0.PORTBADDR10
address_b[10] => ram_block15a1.PORTBADDR10
address_b[10] => ram_block15a2.PORTBADDR10
address_b[10] => ram_block15a3.PORTBADDR10
address_b[10] => ram_block15a4.PORTBADDR10
address_b[10] => ram_block15a5.PORTBADDR10
address_b[10] => ram_block15a6.PORTBADDR10
address_b[10] => ram_block15a7.PORTBADDR10
address_b[10] => ram_block15a8.PORTBADDR10
address_b[10] => ram_block15a9.PORTBADDR10
address_b[10] => ram_block15a10.PORTBADDR10
address_b[10] => ram_block15a11.PORTBADDR10
address_b[10] => ram_block15a12.PORTBADDR10
address_b[10] => ram_block15a13.PORTBADDR10
address_b[10] => ram_block15a14.PORTBADDR10
address_b[10] => ram_block15a15.PORTBADDR10
address_b[10] => ram_block15a16.PORTBADDR10
address_b[10] => ram_block15a17.PORTBADDR10
address_b[10] => ram_block15a18.PORTBADDR10
address_b[10] => ram_block15a19.PORTBADDR10
address_b[10] => ram_block15a20.PORTBADDR10
address_b[10] => ram_block15a21.PORTBADDR10
address_b[10] => ram_block15a22.PORTBADDR10
address_b[10] => ram_block15a23.PORTBADDR10
address_b[10] => ram_block15a24.PORTBADDR10
address_b[10] => ram_block15a25.PORTBADDR10
address_b[10] => ram_block15a26.PORTBADDR10
address_b[10] => ram_block15a27.PORTBADDR10
address_b[10] => ram_block15a28.PORTBADDR10
address_b[10] => ram_block15a29.PORTBADDR10
address_b[10] => ram_block15a30.PORTBADDR10
address_b[10] => ram_block15a31.PORTBADDR10
address_b[11] => ram_block15a0.PORTBADDR11
address_b[11] => ram_block15a1.PORTBADDR11
address_b[11] => ram_block15a2.PORTBADDR11
address_b[11] => ram_block15a3.PORTBADDR11
address_b[11] => ram_block15a4.PORTBADDR11
address_b[11] => ram_block15a5.PORTBADDR11
address_b[11] => ram_block15a6.PORTBADDR11
address_b[11] => ram_block15a7.PORTBADDR11
address_b[11] => ram_block15a8.PORTBADDR11
address_b[11] => ram_block15a9.PORTBADDR11
address_b[11] => ram_block15a10.PORTBADDR11
address_b[11] => ram_block15a11.PORTBADDR11
address_b[11] => ram_block15a12.PORTBADDR11
address_b[11] => ram_block15a13.PORTBADDR11
address_b[11] => ram_block15a14.PORTBADDR11
address_b[11] => ram_block15a15.PORTBADDR11
address_b[11] => ram_block15a16.PORTBADDR11
address_b[11] => ram_block15a17.PORTBADDR11
address_b[11] => ram_block15a18.PORTBADDR11
address_b[11] => ram_block15a19.PORTBADDR11
address_b[11] => ram_block15a20.PORTBADDR11
address_b[11] => ram_block15a21.PORTBADDR11
address_b[11] => ram_block15a22.PORTBADDR11
address_b[11] => ram_block15a23.PORTBADDR11
address_b[11] => ram_block15a24.PORTBADDR11
address_b[11] => ram_block15a25.PORTBADDR11
address_b[11] => ram_block15a26.PORTBADDR11
address_b[11] => ram_block15a27.PORTBADDR11
address_b[11] => ram_block15a28.PORTBADDR11
address_b[11] => ram_block15a29.PORTBADDR11
address_b[11] => ram_block15a30.PORTBADDR11
address_b[11] => ram_block15a31.PORTBADDR11
address_b[12] => address_reg_b[0].DATAIN
address_b[12] => decode_tt6:rden_decode.data[0]
address_b[13] => address_reg_b[1].DATAIN
address_b[13] => decode_tt6:rden_decode.data[1]
address_b[14] => address_reg_b[2].DATAIN
address_b[14] => decode_tt6:rden_decode.data[2]
address_b[15] => address_reg_b[3].DATAIN
address_b[15] => decode_tt6:rden_decode.data[3]
address_b[16] => address_reg_b[4].DATAIN
address_b[16] => decode_tt6:rden_decode.data[4]
clock0 => ram_block15a0.CLK0
clock0 => ram_block15a1.CLK0
clock0 => ram_block15a2.CLK0
clock0 => ram_block15a3.CLK0
clock0 => ram_block15a4.CLK0
clock0 => ram_block15a5.CLK0
clock0 => ram_block15a6.CLK0
clock0 => ram_block15a7.CLK0
clock0 => ram_block15a8.CLK0
clock0 => ram_block15a9.CLK0
clock0 => ram_block15a10.CLK0
clock0 => ram_block15a11.CLK0
clock0 => ram_block15a12.CLK0
clock0 => ram_block15a13.CLK0
clock0 => ram_block15a14.CLK0
clock0 => ram_block15a15.CLK0
clock0 => ram_block15a16.CLK0
clock0 => ram_block15a17.CLK0
clock0 => ram_block15a18.CLK0
clock0 => ram_block15a19.CLK0
clock0 => ram_block15a20.CLK0
clock0 => ram_block15a21.CLK0
clock0 => ram_block15a22.CLK0
clock0 => ram_block15a23.CLK0
clock0 => ram_block15a24.CLK0
clock0 => ram_block15a25.CLK0
clock0 => ram_block15a26.CLK0
clock0 => ram_block15a27.CLK0
clock0 => ram_block15a28.CLK0
clock0 => ram_block15a29.CLK0
clock0 => ram_block15a30.CLK0
clock0 => ram_block15a31.CLK0
clock1 => ram_block15a0.CLK1
clock1 => ram_block15a1.CLK1
clock1 => ram_block15a2.CLK1
clock1 => ram_block15a3.CLK1
clock1 => ram_block15a4.CLK1
clock1 => ram_block15a5.CLK1
clock1 => ram_block15a6.CLK1
clock1 => ram_block15a7.CLK1
clock1 => ram_block15a8.CLK1
clock1 => ram_block15a9.CLK1
clock1 => ram_block15a10.CLK1
clock1 => ram_block15a11.CLK1
clock1 => ram_block15a12.CLK1
clock1 => ram_block15a13.CLK1
clock1 => ram_block15a14.CLK1
clock1 => ram_block15a15.CLK1
clock1 => ram_block15a16.CLK1
clock1 => ram_block15a17.CLK1
clock1 => ram_block15a18.CLK1
clock1 => ram_block15a19.CLK1
clock1 => ram_block15a20.CLK1
clock1 => ram_block15a21.CLK1
clock1 => ram_block15a22.CLK1
clock1 => ram_block15a23.CLK1
clock1 => ram_block15a24.CLK1
clock1 => ram_block15a25.CLK1
clock1 => ram_block15a26.CLK1
clock1 => ram_block15a27.CLK1
clock1 => ram_block15a28.CLK1
clock1 => ram_block15a29.CLK1
clock1 => ram_block15a30.CLK1
clock1 => ram_block15a31.CLK1
clock1 => address_reg_b[4].CLK
clock1 => address_reg_b[3].CLK
clock1 => address_reg_b[2].CLK
clock1 => address_reg_b[1].CLK
clock1 => address_reg_b[0].CLK
clocken1 => decode_tt6:rden_decode.enable
clocken1 => address_reg_b[4].ENA