buffer422.hier_info

一个同步422接口控制器的verilog源程序。

rdclk => dffe5a[13].CLK
rdclk => dffe5a[12].CLK
rdclk => dffe5a[11].CLK
rdclk => dffe5a[10].CLK
rdclk => dffe5a[9].CLK
rdclk => dffe5a[8].CLK
rdclk => dffe5a[7].CLK
rdclk => dffe5a[6].CLK
rdclk => dffe5a[5].CLK
rdclk => dffe5a[4].CLK
rdclk => dffe5a[3].CLK
rdclk => dffe5a[2].CLK
rdclk => dffe5a[1].CLK
rdclk => dffe5a[0].CLK
rdclk => dffe8a[17].CLK
rdclk => dffe8a[16].CLK
rdclk => dffe8a[15].CLK
rdclk => dffe8a[14].CLK
rdclk => dffe8a[13].CLK
rdclk => dffe8a[12].CLK
rdclk => dffe8a[11].CLK
rdclk => dffe8a[10].CLK
rdclk => dffe8a[9].CLK
rdclk => dffe8a[8].CLK
rdclk => dffe8a[7].CLK
rdclk => dffe8a[6].CLK
rdclk => dffe8a[5].CLK
rdclk => dffe8a[4].CLK
rdclk => dffe8a[3].CLK
rdclk => dffe8a[2].CLK
rdclk => dffe8a[1].CLK
rdclk => dffe8a[0].CLK
rdempty <= cs12a[17].DB_MAX_OUTPUT_PORT_TYPE
rdfull <= add_sub_h18:add_sub3.result[17]
rdusedw[0] <= add_sub_h18:add_sub3.result[0]
rdusedw[1] <= add_sub_h18:add_sub3.result[1]
rdusedw[2] <= add_sub_h18:add_sub3.result[2]
rdusedw[3] <= add_sub_h18:add_sub3.result[3]
rdusedw[4] <= add_sub_h18:add_sub3.result[4]
rdusedw[5] <= add_sub_h18:add_sub3.result[5]
rdusedw[6] <= add_sub_h18:add_sub3.result[6]
rdusedw[7] <= add_sub_h18:add_sub3.result[7]
rdusedw[8] <= add_sub_h18:add_sub3.result[8]
rdusedw[9] <= add_sub_h18:add_sub3.result[9]
rdusedw[10] <= add_sub_h18:add_sub3.result[10]
rdusedw[11] <= add_sub_h18:add_sub3.result[11]
rdusedw[12] <= add_sub_h18:add_sub3.result[12]
rdusedw[13] <= add_sub_h18:add_sub3.result[13]
rdusedw[14] <= add_sub_h18:add_sub3.result[14]
rdusedw[15] <= add_sub_h18:add_sub3.result[15]
rdusedw[16] <= add_sub_h18:add_sub3.result[16]
wrclk => dpram_evr:dpram4.inclock
wrclk => cntr_q08:cntr1.clock
wrclk => dffe7a[17].CLK
wrclk => dffe7a[16].CLK
wrclk => dffe7a[15].CLK
wrclk => dffe7a[14].CLK
wrclk => dffe7a[13].CLK
wrclk => dffe7a[12].CLK
wrclk => dffe7a[11].CLK
wrclk => dffe7a[10].CLK
wrclk => dffe7a[9].CLK
wrclk => dffe7a[8].CLK
wrclk => dffe7a[7].CLK
wrclk => dffe7a[6].CLK
wrclk => dffe7a[5].CLK
wrclk => dffe7a[4].CLK
wrclk => dffe7a[3].CLK
wrclk => dffe7a[2].CLK
wrclk => dffe7a[1].CLK
wrclk => dffe7a[0].CLK
wrclk => dffe9a[17].CLK
wrclk => dffe9a[16].CLK
wrclk => dffe9a[15].CLK
wrclk => dffe9a[14].CLK
wrclk => dffe9a[13].CLK
wrclk => dffe9a[12].CLK
wrclk => dffe9a[11].CLK
wrclk => dffe9a[10].CLK
wrclk => dffe9a[9].CLK
wrclk => dffe9a[8].CLK
wrclk => dffe9a[7].CLK
wrclk => dffe9a[6].CLK
wrclk => dffe9a[5].CLK
wrclk => dffe9a[4].CLK
wrclk => dffe9a[3].CLK
wrclk => dffe9a[2].CLK
wrclk => dffe9a[1].CLK
wrclk => dffe9a[0].CLK
wrempty <= cs11a[17].DB_MAX_OUTPUT_PORT_TYPE
wrfull <= cs10a[0].DB_MAX_OUTPUT_PORT_TYPE
wrusedw[0] <= add_sub_bg8:add_sub2.result[0]
wrusedw[1] <= add_sub_bg8:add_sub2.result[1]
wrusedw[2] <= add_sub_bg8:add_sub2.result[2]
wrusedw[3] <= add_sub_bg8:add_sub2.result[3]
wrusedw[4] <= add_sub_bg8:add_sub2.result[4]
wrusedw[5] <= add_sub_bg8:add_sub2.result[5]
wrusedw[6] <= add_sub_bg8:add_sub2.result[6]
wrusedw[7] <= add_sub_bg8:add_sub2.result[7]
wrusedw[8] <= add_sub_bg8:add_sub2.result[8]
wrusedw[9] <= add_sub_bg8:add_sub2.result[9]
wrusedw[10] <= add_sub_bg8:add_sub2.result[10]
wrusedw[11] <= add_sub_bg8:add_sub2.result[11]
wrusedw[12] <= add_sub_bg8:add_sub2.result[12]
wrusedw[13] <= add_sub_bg8:add_sub2.result[13]
wrusedw[14] <= add_sub_bg8:add_sub2.result[14]
wrusedw[15] <= add_sub_bg8:add_sub2.result[15]
wrusedw[16] <= add_sub_bg8:add_sub2.result[16]


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4
data[0] => altsyncram_pof1:altsyncram14.data_a[0]
inclock => altsyncram_pof1:altsyncram14.clock0
outclock => altsyncram_pof1:altsyncram14.clock1
outclocken => altsyncram_pof1:altsyncram14.clocken1
q[0] <= altsyncram_pof1:altsyncram14.q_b[0]
rdaddress[0] => altsyncram_pof1:altsyncram14.address_b[0]
rdaddress[1] => altsyncram_pof1:altsyncram14.address_b[1]
rdaddress[2] => altsyncram_pof1:altsyncram14.address_b[2]
rdaddress[3] => altsyncram_pof1:altsyncram14.address_b[3]
rdaddress[4] => altsyncram_pof1:altsyncram14.address_b[4]
rdaddress[5] => altsyncram_pof1:altsyncram14.address_b[5]
rdaddress[6] => altsyncram_pof1:altsyncram14.address_b[6]
rdaddress[7] => altsyncram_pof1:altsyncram14.address_b[7]
rdaddress[8] => altsyncram_pof1:altsyncram14.address_b[8]
rdaddress[9] => altsyncram_pof1:altsyncram14.address_b[9]
rdaddress[10] => altsyncram_pof1:altsyncram14.address_b[10]
rdaddress[11] => altsyncram_pof1:altsyncram14.address_b[11]
rdaddress[12] => altsyncram_pof1:altsyncram14.address_b[12]
rdaddress[13] => altsyncram_pof1:altsyncram14.address_b[13]
rdaddress[14] => altsyncram_pof1:altsyncram14.address_b[14]
rdaddress[15] => altsyncram_pof1:altsyncram14.address_b[15]
rdaddress[16] => altsyncram_pof1:altsyncram14.address_b[16]
wraddress[0] => altsyncram_pof1:altsyncram14.address_a[0]
wraddress[1] => altsyncram_pof1:altsyncram14.address_a[1]
wraddress[2] => altsyncram_pof1:altsyncram14.address_a[2]
wraddress[3] => altsyncram_pof1:altsyncram14.address_a[3]
wraddress[4] => altsyncram_pof1:altsyncram14.address_a[4]
wraddress[5] => altsyncram_pof1:altsyncram14.address_a[5]
wraddress[6] => altsyncram_pof1:altsyncram14.address_a[6]
wraddress[7] => altsyncram_pof1:altsyncram14.address_a[7]
wraddress[8] => altsyncram_pof1:altsyncram14.address_a[8]
wraddress[9] => altsyncram_pof1:altsyncram14.address_a[9]
wraddress[10] => altsyncram_pof1:altsyncram14.address_a[10]
wraddress[11] => altsyncram_pof1:altsyncram14.address_a[11]
wraddress[12] => altsyncram_pof1:altsyncram14.address_a[12]
wraddress[13] => altsyncram_pof1:altsyncram14.address_a[13]
wraddress[14] => altsyncram_pof1:altsyncram14.address_a[14]
wraddress[15] => altsyncram_pof1:altsyncram14.address_a[15]
wraddress[16] => altsyncram_pof1:altsyncram14.address_a[16]
wren => altsyncram_pof1:altsyncram14.wren_a


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14
address_a[0] => ram_block15a0.PORTAADDR
address_a[0] => ram_block15a1.PORTAADDR
address_a[0] => ram_block15a2.PORTAADDR
address_a[0] => ram_block15a3.PORTAADDR
address_a[0] => ram_block15a4.PORTAADDR
address_a[0] => ram_block15a5.PORTAADDR
address_a[0] => ram_block15a6.PORTAADDR
address_a[0] => ram_block15a7.PORTAADDR
address_a[0] => ram_block15a8.PORTAADDR
address_a[0] => ram_block15a9.PORTAADDR
address_a[0] => ram_block15a10.PORTAADDR
address_a[0] => ram_block15a11.PORTAADDR
address_a[0] => ram_block15a12.PORTAADDR
address_a[0] => ram_block15a13.PORTAADDR
address_a[0] => ram_block15a14.PORTAADDR
address_a[0] => ram_block15a15.PORTAADDR
address_a[0] => ram_block15a16.PORTAADDR
address_a[0] => ram_block15a17.PORTAADDR
address_a[0] => ram_block15a18.PORTAADDR
address_a[0] => ram_block15a19.PORTAADDR
address_a[0] => ram_block15a20.PORTAADDR
address_a[0] => ram_block15a21.PORTAADDR
address_a[0] => ram_block15a22.PORTAADDR
address_a[0] => ram_block15a23.PORTAADDR
address_a[0] => ram_block15a24.PORTAADDR
address_a[0] => ram_block15a25.PORTAADDR
address_a[0] => ram_block15a26.PORTAADDR
address_a[0] => ram_block15a27.PORTAADDR
address_a[0] => ram_block15a28.PORTAADDR
address_a[0] => ram_block15a29.PORTAADDR
address_a[0] => ram_block15a30.PORTAADDR
address_a[0] => ram_block15a31.PORTAADDR
address_a[1] => ram_block15a0.PORTAADDR1
address_a[1] => ram_block15a1.PORTAADDR1
address_a[1] => ram_block15a2.PORTAADDR1
address_a[1] => ram_block15a3.PORTAADDR1
address_a[1] => ram_block15a4.PORTAADDR1
address_a[1] => ram_block15a5.PORTAADDR1
address_a[1] => ram_block15a6.PORTAADDR1
address_a[1] => ram_block15a7.PORTAADDR1
address_a[1] => ram_block15a8.PORTAADDR1
address_a[1] => ram_block15a9.PORTAADDR1
address_a[1] => ram_block15a10.PORTAADDR1
address_a[1] => ram_block15a11.PORTAADDR1
address_a[1] => ram_block15a12.PORTAADDR1
address_a[1] => ram_block15a13.PORTAADDR1
address_a[1] => ram_block15a14.PORTAADDR1
address_a[1] => ram_block15a15.PORTAADDR1
address_a[1] => ram_block15a16.PORTAADDR1
address_a[1] => ram_block15a17.PORTAADDR1
address_a[1] => ram_block15a18.PORTAADDR1
address_a[1] => ram_block15a19.PORTAADDR1
address_a[1] => ram_block15a20.PORTAADDR1
address_a[1] => ram_block15a21.PORTAADDR1
address_a[1] => ram_block15a22.PORTAADDR1
address_a[1] => ram_block15a23.PORTAADDR1
address_a[1] => ram_block15a24.PORTAADDR1
address_a[1] => ram_block15a25.PORTAADDR1
address_a[1] => ram_block15a26.PORTAADDR1
address_a[1] => ram_block15a27.PORTAADDR1
address_a[1] => ram_block15a28.PORTAADDR1
address_a[1] => ram_block15a29.PORTAADDR1
address_a[1] => ram_block15a30.PORTAADDR1
address_a[1] => ram_block15a31.PORTAADDR1
address_a[2] => ram_block15a0.PORTAADDR2
address_a[2] => ram_block15a1.PORTAADDR2
address_a[2] => ram_block15a2.PORTAADDR2
address_a[2] => ram_block15a3.PORTAADDR2
address_a[2] => ram_block15a4.PORTAADDR2
address_a[2] => ram_block15a5.PORTAADDR2
address_a[2] => ram_block15a6.PORTAADDR2
address_a[2] => ram_block15a7.PORTAADDR2
address_a[2] => ram_block15a8.PORTAADDR2
address_a[2] => ram_block15a9.PORTAADDR2
address_a[2] => ram_block15a10.PORTAADDR2
address_a[2] => ram_block15a11.PORTAADDR2
address_a[2] => ram_block15a12.PORTAADDR2
address_a[2] => ram_block15a13.PORTAADDR2
address_a[2] => ram_block15a14.PORTAADDR2
address_a[2] => ram_block15a15.PORTAADDR2
address_a[2] => ram_block15a16.PORTAADDR2
address_a[2] => ram_block15a17.PORTAADDR2
address_a[2] => ram_block15a18.PORTAADDR2
address_a[2] => ram_block15a19.PORTAADDR2
address_a[2] => ram_block15a20.PORTAADDR2
address_a[2] => ram_block15a21.PORTAADDR2
address_a[2] => ram_block15a22.PORTAADDR2
address_a[2] => ram_block15a23.PORTAADDR2
address_a[2] => ram_block15a24.PORTAADDR2
address_a[2] => ram_block15a25.PORTAADDR2
address_a[2] => ram_block15a26.PORTAADDR2
address_a[2] => ram_block15a27.PORTAADDR2
address_a[2] => ram_block15a28.PORTAADDR2
address_a[2] => ram_block15a29.PORTAADDR2
address_a[2] => ram_block15a30.PORTAADDR2
address_a[2] => ram_block15a31.PORTAADDR2
address_a[3] => ram_block15a0.PORTAADDR3
address_a[3] => ram_block15a1.PORTAADDR3
address_a[3] => ram_block15a2.PORTAADDR3
address_a[3] => ram_block15a3.PORTAADDR3
address_a[3] => ram_block15a4.PORTAADDR3
address_a[3] => ram_block15a5.PORTAADDR3
address_a[3] => ram_block15a6.PORTAADDR3
address_a[3] => ram_block15a7.PORTAADDR3
address_a[3] => ram_block15a8.PORTAADDR3
address_a[3] => ram_block15a9.PORTAADDR3
address_a[3] => ram_block15a10.PORTAADDR3
address_a[3] => ram_block15a11.PORTAADDR3
address_a[3] => ram_block15a12.PORTAADDR3
address_a[3] => ram_block15a13.PORTAADDR3
address_a[3] => ram_block15a14.PORTAADDR3
address_a[3] => ram_block15a15.PORTAADDR3
address_a[3] => ram_block15a16.PORTAADDR3
address_a[3] => ram_block15a17.PORTAADDR3
address_a[3] => ram_block15a18.PORTAADDR3
address_a[3] => ram_block15a19.PORTAADDR3
address_a[3] => ram_block15a20.PORTAADDR3
address_a[3] => ram_block15a21.PORTAADDR3
address_a[3] => ram_block15a22.PORTAADDR3
address_a[3] => ram_block15a23.PORTAADDR3
address_a[3] => ram_block15a24.PORTAADDR3
address_a[3] => ram_block15a25.PORTAADDR3
address_a[3] => ram_block15a26.PORTAADDR3
address_a[3] => ram_block15a27.PORTAADDR3
address_a[3] => ram_block15a28.PORTAADDR3
address_a[3] => ram_block15a29.PORTAADDR3
address_a[3] => ram_block15a30.PORTAADDR3
address_a[3] => ram_block15a31.PORTAADDR3
address_a[4] => ram_block15a0.PORTAADDR4
address_a[4] => ram_block15a1.PORTAADDR4
address_a[4] => ram_block15a2.PORTAADDR4
address_a[4] => ram_block15a3.PORTAADDR4
address_a[4] => ram_block15a4.PORTAADDR4
address_a[4] => ram_block15a5.PORTAADDR4
address_a[4] => ram_block15a6.PORTAADDR4
address_a[4] => ram_block15a7.PORTAADDR4
address_a[4] => ram_block15a8.PORTAADDR4
address_a[4] => ram_block15a9.PORTAADDR4
address_a[4] => ram_block15a10.PORTAADDR4
address_a[4] => ram_block15a11.PORTAADDR4
address_a[4] => ram_block15a12.PORTAADDR4
address_a[4] => ram_block15a13.PORTAADDR4
address_a[4] => ram_block15a14.PORTAADDR4
address_a[4] => ram_block15a15.PORTAADDR4
address_a[4] => ram_block15a16.PORTAADDR4
address_a[4] => ram_block15a17.PORTAADDR4
address_a[4] => ram_block15a18.PORTAADDR4
address_a[4] => ram_block15a19.PORTAADDR4
address_a[4] => ram_block15a20.PORTAADDR4
address_a[4] => ram_block15a21.PORTAADDR4
address_a[4] => ram_block15a22.PORTAADDR4
address_a[4] => ram_block15a23.PORTAADDR4
address_a[4] => ram_block15a24.PORTAADDR4
address_a[4] => ram_block15a25.PORTAADDR4
address_a[4] => ram_block15a26.PORTAADDR4
address_a[4] => ram_block15a27.PORTAADDR4
address_a[4] => ram_block15a28.PORTAADDR4
address_a[4] => ram_block15a29.PORTAADDR4
address_a[4] => ram_block15a30.PORTAADDR4
address_a[4] => ram_block15a31.PORTAADDR4
address_a[5] => ram_block15a0.PORTAADDR5
address_a[5] => ram_block15a1.PORTAADDR5
address_a[5] => ram_block15a2.PORTAADDR5
address_a[5] => ram_block15a3.PORTAADDR5
address_a[5] => ram_block15a4.PORTAADDR5
address_a[5] => ram_block15a5.PORTAADDR5
address_a[5] => ram_block15a6.PORTAADDR5
address_a[5] => ram_block15a7.PORTAADDR5
address_a[5] => ram_block15a8.PORTAADDR5
address_a[5] => ram_block15a9.PORTAADDR5
address_a[5] => ram_block15a10.PORTAADDR5
address_a[5] => ram_block15a11.PORTAADDR5
address_a[5] => ram_block15a12.PORTAADDR5
address_a[5] => ram_block15a13.PORTAADDR5
address_a[5] => ram_block15a14.PORTAADDR5
address_a[5] => ram_block15a15.PORTAADDR5
address_a[5] => ram_block15a16.PORTAADDR5
address_a[5] => ram_block15a17.PORTAADDR5
address_a[5] => ram_block15a18.PORTAADDR5
address_a[5] => ram_block15a19.PORTAADDR5
address_a[5] => ram_block15a20.PORTAADDR5
address_a[5] => ram_block15a21.PORTAADDR5