buffer422.hier_info

一个同步422接口控制器的verilog源程序。

|buffer422
clk_out <= buff_control:inst.clout
rst => buff_control:inst.rst
clk => buff_control:inst.clk
data_in => buff_control:inst.data_in
clk_in => buff_control:inst.clk_in
data_out <= buff_control:inst.dout
rdreq <= buff_control:inst.rdreq


|buffer422|buff_control:inst
rst => rdreq~reg0.ACLR
rst => dout~reg0.ACLR
rst => clkdiv.ACLR
rst => clk_reg1.ACLR
rst => clk_reg2.ACLR
rst => clk_reg3.ACLR
rst => dat_reg.ACLR
rst => dat_reg1.ACLR
rst => dat_reg2.ACLR
rst => dat_reg3.ACLR
rst => clk_reg.ACLR
rst => clcnt[1].ACLR
rst => clcnt[0].ACLR
rst => clcnt[2].ACLR
rst => clen.ACLR
rst => dly_cnt[26].ACLR
rst => dly_cnt[25].ACLR
rst => dly_cnt[24].ACLR
rst => dly_cnt[23].ACLR
rst => dly_cnt[22].ACLR
rst => dly_cnt[21].ACLR
rst => dly_cnt[20].ACLR
rst => dly_cnt[19].ACLR
rst => dly_cnt[18].ACLR
rst => dly_cnt[17].ACLR
rst => dly_cnt[16].ACLR
rst => dly_cnt[15].ACLR
rst => dly_cnt[14].ACLR
rst => dly_cnt[13].ACLR
rst => dly_cnt[12].ACLR
rst => dly_cnt[11].ACLR
rst => dly_cnt[10].ACLR
rst => dly_cnt[9].ACLR
rst => dly_cnt[8].ACLR
rst => dly_cnt[7].ACLR
rst => dly_cnt[6].ACLR
rst => dly_cnt[5].ACLR
rst => dly_cnt[4].ACLR
rst => dly_cnt[3].ACLR
rst => dly_cnt[2].ACLR
rst => dly_cnt[1].ACLR
rst => dly_cnt[0].ACLR
rst => dly_cnt[27].ACLR
rst => active.ACLR
rst => dd_active.ACLR
rst => d_active.ACLR
rst => infos_sel.ACLR
rst => infoe_sel.ACLR
rst => cnt[3].ACLR
rst => cnt[2].ACLR
rst => cnt[1].ACLR
rst => cnt[0].ACLR
rst => cnt[4].ACLR
rst => infos[30].PRESET
rst => infos[29].PRESET
rst => infos[28].PRESET
rst => infos[27].PRESET
rst => infos[26].PRESET
rst => infos[25].PRESET
rst => infos[24].PRESET
rst => infos[23].PRESET
rst => infos[22].PRESET
rst => infos[21].PRESET
rst => infos[20].PRESET
rst => infos[19].PRESET
rst => infos[18].PRESET
rst => infos[17].PRESET
rst => infos[16].PRESET
rst => infos[15].PRESET
rst => infos[14].PRESET
rst => infos[13].PRESET
rst => infos[12].PRESET
rst => infos[11].PRESET
rst => infos[10].PRESET
rst => infos[9].ACLR
rst => infos[8].ACLR
rst => infos[7].ACLR
rst => infos[6].ACLR
rst => infos[5].ACLR
rst => infos[4].PRESET
rst => infos[3].PRESET
rst => infos[2].PRESET
rst => infos[1].ACLR
rst => infos[0].PRESET
rst => infos[31].PRESET
rst => infoe[30].PRESET
rst => infoe[29].PRESET
rst => infoe[28].PRESET
rst => infoe[27].PRESET
rst => infoe[26].PRESET
rst => infoe[25].PRESET
rst => infoe[24].PRESET
rst => infoe[23].PRESET
rst => infoe[22].PRESET
rst => infoe[21].PRESET
rst => infoe[20].PRESET
rst => infoe[19].PRESET
rst => infoe[18].PRESET
rst => infoe[17].PRESET
rst => infoe[16].PRESET
rst => infoe[15].ACLR
rst => infoe[14].ACLR
rst => infoe[13].ACLR
rst => infoe[12].PRESET
rst => infoe[11].PRESET
rst => infoe[10].ACLR
rst => infoe[9].PRESET
rst => infoe[8].ACLR
rst => infoe[7].PRESET
rst => infoe[6].PRESET
rst => infoe[5].ACLR
rst => infoe[4].ACLR
rst => infoe[3].PRESET
rst => infoe[2].PRESET
rst => infoe[1].PRESET
rst => infoe[0].PRESET
rst => infoe[31].PRESET
rst => aclr.DATAIN
rst => wrclk~reg0.ENA
rst => data~reg0.ENA
clk => clk_reg1.CLK
clk => clk_reg2.CLK
clk => clk_reg3.CLK
clk => dat_reg.CLK
clk => dat_reg1.CLK
clk => dat_reg2.CLK
clk => dat_reg3.CLK
clk => wrclk~reg0.CLK
clk => data~reg0.CLK
clk => clcnt[2].CLK
clk => clcnt[1].CLK
clk => clcnt[0].CLK
clk => clen.CLK
clk => dly_cnt[27].CLK
clk => dly_cnt[26].CLK
clk => dly_cnt[25].CLK
clk => dly_cnt[24].CLK
clk => dly_cnt[23].CLK
clk => dly_cnt[22].CLK
clk => dly_cnt[21].CLK
clk => dly_cnt[20].CLK
clk => dly_cnt[19].CLK
clk => dly_cnt[18].CLK
clk => dly_cnt[17].CLK
clk => dly_cnt[16].CLK
clk => dly_cnt[15].CLK
clk => dly_cnt[14].CLK
clk => dly_cnt[13].CLK
clk => dly_cnt[12].CLK
clk => dly_cnt[11].CLK
clk => dly_cnt[10].CLK
clk => dly_cnt[9].CLK
clk => dly_cnt[8].CLK
clk => dly_cnt[7].CLK
clk => dly_cnt[6].CLK
clk => dly_cnt[5].CLK
clk => dly_cnt[4].CLK
clk => dly_cnt[3].CLK
clk => dly_cnt[2].CLK
clk => dly_cnt[1].CLK
clk => dly_cnt[0].CLK
clk => clkdiv.CLK
clk => clk_reg.CLK
tdin => dout~0.DATAB
rdusedw[0] => Equal3.IN16
rdusedw[1] => Equal3.IN15
rdusedw[2] => Equal3.IN14
rdusedw[3] => Equal3.IN13
rdusedw[4] => Equal3.IN12
rdusedw[5] => Equal3.IN11
rdusedw[6] => Equal3.IN10
rdusedw[7] => Equal3.IN9
rdusedw[8] => Equal3.IN8
rdusedw[9] => Equal3.IN7
rdusedw[10] => Equal3.IN6
rdusedw[11] => Equal3.IN5
rdusedw[12] => Equal3.IN4
rdusedw[13] => Equal3.IN3
rdusedw[14] => Equal3.IN2
rdusedw[15] => Equal3.IN1
rdusedw[16] => active~0.OUTPUTSELECT
rdusedw[16] => Equal3.IN0
data_in => dat_reg.DATAIN
clk_in => clk_reg.DATAIN
aclr <= rst.DB_MAX_OUTPUT_PORT_TYPE
rdreq <= rdreq~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout <= dout~reg0.DB_MAX_OUTPUT_PORT_TYPE
clout <= clout~2.DB_MAX_OUTPUT_PORT_TYPE
rdclk <= clkdiv.DB_MAX_OUTPUT_PORT_TYPE
data <= data~reg0.DB_MAX_OUTPUT_PORT_TYPE
wrclk <= wrclk~reg0.DB_MAX_OUTPUT_PORT_TYPE


|buffer422|lpm_fifo0:inst1
aclr => aclr~0.IN1
data[0] => data[0]~0.IN1
rdclk => rdclk~0.IN1
rdreq => rdreq~0.IN1
wrclk => wrclk~0.IN1
wrreq => wrreq~0.IN1
q[0] <= dcfifo:dcfifo_component.q
rdusedw[0] <= dcfifo:dcfifo_component.rdusedw
rdusedw[1] <= dcfifo:dcfifo_component.rdusedw
rdusedw[2] <= dcfifo:dcfifo_component.rdusedw
rdusedw[3] <= dcfifo:dcfifo_component.rdusedw
rdusedw[4] <= dcfifo:dcfifo_component.rdusedw
rdusedw[5] <= dcfifo:dcfifo_component.rdusedw
rdusedw[6] <= dcfifo:dcfifo_component.rdusedw
rdusedw[7] <= dcfifo:dcfifo_component.rdusedw
rdusedw[8] <= dcfifo:dcfifo_component.rdusedw
rdusedw[9] <= dcfifo:dcfifo_component.rdusedw
rdusedw[10] <= dcfifo:dcfifo_component.rdusedw
rdusedw[11] <= dcfifo:dcfifo_component.rdusedw
rdusedw[12] <= dcfifo:dcfifo_component.rdusedw
rdusedw[13] <= dcfifo:dcfifo_component.rdusedw
rdusedw[14] <= dcfifo:dcfifo_component.rdusedw
rdusedw[15] <= dcfifo:dcfifo_component.rdusedw
rdusedw[16] <= dcfifo:dcfifo_component.rdusedw


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component
data[0] => dcfifo_so91:auto_generated.data[0]
q[0] <= dcfifo_so91:auto_generated.q[0]
rdclk => dcfifo_so91:auto_generated.rdclk
rdreq => dcfifo_so91:auto_generated.rdreq
wrclk => dcfifo_so91:auto_generated.wrclk
wrreq => dcfifo_so91:auto_generated.wrreq
aclr => dcfifo_so91:auto_generated.aclr
rdempty <= <UNC>
rdfull <= <UNC>
wrempty <= <GND>
wrfull <= <GND>
rdusedw[0] <= dcfifo_so91:auto_generated.rdusedw[0]
rdusedw[1] <= dcfifo_so91:auto_generated.rdusedw[1]
rdusedw[2] <= dcfifo_so91:auto_generated.rdusedw[2]
rdusedw[3] <= dcfifo_so91:auto_generated.rdusedw[3]
rdusedw[4] <= dcfifo_so91:auto_generated.rdusedw[4]
rdusedw[5] <= dcfifo_so91:auto_generated.rdusedw[5]
rdusedw[6] <= dcfifo_so91:auto_generated.rdusedw[6]
rdusedw[7] <= dcfifo_so91:auto_generated.rdusedw[7]
rdusedw[8] <= dcfifo_so91:auto_generated.rdusedw[8]
rdusedw[9] <= dcfifo_so91:auto_generated.rdusedw[9]
rdusedw[10] <= dcfifo_so91:auto_generated.rdusedw[10]
rdusedw[11] <= dcfifo_so91:auto_generated.rdusedw[11]
rdusedw[12] <= dcfifo_so91:auto_generated.rdusedw[12]
rdusedw[13] <= dcfifo_so91:auto_generated.rdusedw[13]
rdusedw[14] <= dcfifo_so91:auto_generated.rdusedw[14]
rdusedw[15] <= dcfifo_so91:auto_generated.rdusedw[15]
rdusedw[16] <= dcfifo_so91:auto_generated.rdusedw[16]
wrusedw[0] <= <GND>
wrusedw[1] <= <GND>
wrusedw[2] <= <GND>
wrusedw[3] <= <GND>
wrusedw[4] <= <GND>
wrusedw[5] <= <GND>
wrusedw[6] <= <GND>
wrusedw[7] <= <GND>
wrusedw[8] <= <GND>
wrusedw[9] <= <GND>
wrusedw[10] <= <GND>
wrusedw[11] <= <GND>
wrusedw[12] <= <GND>
wrusedw[13] <= <GND>
wrusedw[14] <= <GND>
wrusedw[15] <= <GND>
wrusedw[16] <= <GND>


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated
aclr => alt_sync_fifo_fjm:sync_fifo.aclr
data[0] => alt_sync_fifo_fjm:sync_fifo.data[0]
q[0] <= alt_sync_fifo_fjm:sync_fifo.q[0]
rdclk => alt_sync_fifo_fjm:sync_fifo.rdclk
rdempty <= alt_sync_fifo_fjm:sync_fifo.rdempty
rdfull <= alt_sync_fifo_fjm:sync_fifo.rdfull
rdreq => alt_sync_fifo_fjm:sync_fifo.rdreq
rdusedw[0] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[0]
rdusedw[1] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[1]
rdusedw[2] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[2]
rdusedw[3] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[3]
rdusedw[4] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[4]
rdusedw[5] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[5]
rdusedw[6] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[6]
rdusedw[7] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[7]
rdusedw[8] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[8]
rdusedw[9] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[9]
rdusedw[10] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[10]
rdusedw[11] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[11]
rdusedw[12] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[12]
rdusedw[13] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[13]
rdusedw[14] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[14]
rdusedw[15] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[15]
rdusedw[16] <= alt_sync_fifo_fjm:sync_fifo.rdusedw[16]
wrclk => alt_sync_fifo_fjm:sync_fifo.wrclk
wrempty <= alt_sync_fifo_fjm:sync_fifo.wrempty
wrfull <= alt_sync_fifo_fjm:sync_fifo.wrfull
wrreq => alt_sync_fifo_fjm:sync_fifo.wrreq
wrusedw[0] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[0]
wrusedw[1] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[1]
wrusedw[2] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[2]
wrusedw[3] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[3]
wrusedw[4] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[4]
wrusedw[5] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[5]
wrusedw[6] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[6]
wrusedw[7] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[7]
wrusedw[8] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[8]
wrusedw[9] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[9]
wrusedw[10] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[10]
wrusedw[11] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[11]
wrusedw[12] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[12]
wrusedw[13] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[13]
wrusedw[14] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[14]
wrusedw[15] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[15]
wrusedw[16] <= alt_sync_fifo_fjm:sync_fifo.wrusedw[16]


|buffer422|lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo
aclr => cntr_q08:cntr1.aclr
data[0] => dpram_evr:dpram4.data[0]
q[0] <= dpram_evr:dpram4.q[0]
rdclk => dpram_evr:dpram4.outclock
rdclk => dffe5a[17].CLK
rdclk => dffe5a[16].CLK
rdclk => dffe5a[15].CLK
rdclk => dffe5a[14].CLK