alt_sync_fifo_bdm.tdf

一个同步422接口控制器的verilog源程序。

--alt_sync_fifo DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=128 LPM_SHOWAHEAD="OFF" LPM_WIDTH=1 LPM_WIDTHU=7 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdempty rdfull rdreq rdusedw wrclk wrempty wrfull wrreq wrusedw
--VERSION_BEGIN 6.0 cbx_a_gray2bin 2006:02:28:17:43:38:SJ cbx_a_graycounter 2006:03:13:11:03:08:SJ cbx_altdpram 2006:01:09:10:52:42:SJ cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_dcfifo 2006:03:30:14:19:28:SJ cbx_fifo_common 2006:01:09:11:23:34:SJ cbx_flex10ke 2006:01:09:11:13:48:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_scfifo 2006:01:09:11:24:10:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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FUNCTION dpram_ttr (data[0..0], inclock, outclock, outclocken, rdaddress[6..0], wraddress[6..0], wren)
RETURNS ( q[0..0]);
FUNCTION carry_sum (cin, sin)
RETURNS ( cout, sout);
FUNCTION add_sub_qe8 (dataa[6..0], datab[6..0])
RETURNS ( cout, result[6..0]);
FUNCTION add_sub_008 (dataa[7..0], datab[7..0])
RETURNS ( result[7..0]);
FUNCTION cntr_9v7 (aclr, clock, cnt_en)
RETURNS ( q[7..0]);

--synthesis_resources = lut 82 M4K 1 
SUBDESIGN alt_sync_fifo_bdm
( 
	aclr	:	input;
	data[0..0]	:	input;
	q[0..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdfull	:	output;
	rdreq	:	input;
	rdusedw[6..0]	:	output;
	wrclk	:	input;
	wrempty	:	output;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[6..0]	:	output;
) 
VARIABLE 
	dpram4 : dpram_ttr;
	cs10a[1..0] : carry_sum;
	cs11a[7..0] : carry_sum;
	cs12a[7..0] : carry_sum;
	cs13 : carry_sum;
	cs6a[7..0] : carry_sum;
	dffe5a[7..0] : dffe;
	dffe7a[7..0] : dffe;
	dffe8a[7..0] : dffe;
	dffe9a[7..0] : dffe;
	add_sub2 : add_sub_qe8;
	add_sub3 : add_sub_008;
	cntr1 : cntr_9v7;
	fast_feed_read	: WIRE;
	read_count_actual[7..0]	: WIRE;
	read_delay_stratix[7..0]	: WIRE;

BEGIN 
	dpram4.data[] = data[];
	dpram4.inclock = wrclk;
	dpram4.outclock = rdclk;
	dpram4.outclocken = cs13.sout;
	dpram4.rdaddress[6..0] = read_count_actual[6..0];
	dpram4.wraddress[6..0] = cntr1.q[6..0];
	dpram4.wren = cs10a[1..1].sout;
	cs10a[].cin = ( ((! cs10a[0..0].cout) & wrreq), ((! (cntr1.q[7..7] $ dffe9a[7..7].Q)) $ add_sub2.cout));
	cs10a[].sin = ( ((! cs10a[0..0].cout) & wrreq), ((! (cntr1.q[7..7] $ dffe9a[7..7].Q)) $ add_sub2.cout));
	cs11a[].cin = ( ((! (cntr1.q[7..1] $ dffe9a[7..1].Q)) & cs11a[6..0].cout), (! (cntr1.q[0..0] $ dffe9a[0..0].Q)));
	cs11a[].sin = ( ((! (cntr1.q[7..1] $ dffe9a[7..1].Q)) & cs11a[6..0].cout), (! (cntr1.q[0..0] $ dffe9a[0..0].Q)));
	cs12a[].cin = ( ((! (dffe8a[7..1].Q $ read_delay_stratix[7..1])) & cs12a[6..0].cout), (! (dffe8a[0..0].Q $ read_delay_stratix[0..0])));
	cs12a[].sin = ( ((! (dffe8a[7..1].Q $ read_delay_stratix[7..1])) & cs12a[6..0].cout), (! (dffe8a[0..0].Q $ read_delay_stratix[0..0])));
	cs13.cin = ((! cs12a[7..7].cout) & rdreq);
	cs13.sin = ((! cs12a[7..7].cout) & rdreq);
	cs6a[].cin = ( (read_count_actual[7..1] & cs6a[6..0].cout), (fast_feed_read & read_count_actual[0..0]));
	cs6a[].sin = ( (read_count_actual[7..1] $ cs6a[6..0].cout), (fast_feed_read $ read_count_actual[0..0]));
	dffe5a[].CLK = rdclk;
	dffe5a[].CLRN = (! aclr);
	dffe5a[].D = cs6a[].sout;
	dffe7a[].CLK = wrclk;
	dffe7a[].CLRN = (! aclr);
	dffe7a[].D = cntr1.q[];
	dffe8a[].CLK = rdclk;
	dffe8a[].CLRN = (! aclr);
	dffe8a[].D = dffe7a[].Q;
	dffe9a[].CLK = wrclk;
	dffe9a[].CLRN = (! aclr);
	dffe9a[].D = read_delay_stratix[];
	add_sub2.dataa[6..0] = cntr1.q[6..0];
	add_sub2.datab[6..0] = dffe9a[6..0].Q;
	add_sub3.dataa[] = dffe8a[].Q;
	add_sub3.datab[] = read_delay_stratix[];
	cntr1.aclr = aclr;
	cntr1.clock = wrclk;
	cntr1.cnt_en = cs10a[1..1].sout;
	fast_feed_read = cs13.cout;
	q[] = dpram4.q[];
	rdempty = cs12a[7..7].sout;
	rdfull = add_sub3.result[7..7];
	rdusedw[6..0] = add_sub3.result[6..0];
	read_count_actual[] = dffe5a[].Q;
	read_delay_stratix[] = read_count_actual[];
	wrempty = cs11a[7..7].sout;
	wrfull = cs10a[0..0].sout;
	wrusedw[6..0] = add_sub2.result[6..0];
END;
--VALID FILE