alt_sync_fifo_tfm.tdf

一个同步422接口控制器的verilog源程序。

--alt_sync_fifo DEVICE_FAMILY="FLEX10K" LPM_NUMWORDS=131072 LPM_SHOWAHEAD="OFF" LPM_WIDTH=1 LPM_WIDTHU=17 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdempty rdfull rdreq rdusedw wrclk wrempty wrfull wrreq wrusedw
--VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


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FUNCTION altdpram (aclr, data[WIDTH-1..0], inclock, inclocken, outclock, outclocken, rdaddress[WIDTHAD-1..0], rden, wraddress[WIDTHAD-1..0], wren)
WITH ( 	INDATA_ACLR,	INDATA_REG,	LPM_FILE,	lpm_hint,	MAXIMUM_DEPTH,	NUMWORDS,	OUTDATA_ACLR,	OUTDATA_REG,	RDADDRESS_ACLR,	RDADDRESS_REG,	RDCONTROL_ACLR,	RDCONTROL_REG,	USE_EAB,	WIDTH,	WIDTHAD,	WRADDRESS_ACLR,	WRADDRESS_REG,	WRCONTROL_ACLR,	WRCONTROL_REG) 
RETURNS ( q[WIDTH-1..0]);
FUNCTION carry_sum (cin, sin)
RETURNS ( cout, sout);
FUNCTION add_sub_pc8 (dataa[16..0], datab[16..0])
RETURNS ( cout, result[16..0]);
FUNCTION add_sub_vt7 (dataa[17..0], datab[17..0])
RETURNS ( result[17..0]);
FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown)
WITH ( 	lpm_avalue,	lpm_direction,	lpm_modulus,	lpm_svalue,	lpm_width) 
RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]);

--synthesis_resources = altdpram 1 lpm_counter 1 lut 126 
SUBDESIGN alt_sync_fifo_tfm
( 
	aclr	:	input;
	data[0..0]	:	input;
	q[0..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdfull	:	output;
	rdreq	:	input;
	rdusedw[16..0]	:	output;
	wrclk	:	input;
	wrempty	:	output;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[16..0]	:	output;
) 
VARIABLE 
	dpram4 : altdpram
		WITH (
			OUTDATA_REG = "OUTCLOCK",
			RDCONTROL_ACLR = "OFF",
			RDCONTROL_REG = "UNREGISTERED",
			USE_EAB = "ON",
			WIDTH = 1,
			WIDTHAD = 17
		);
	cs11a[1..0] : carry_sum;
	cs12a[17..0] : carry_sum;
	cs13a[17..0] : carry_sum;
	cs14 : carry_sum;
	cs6a[17..0] : carry_sum;
	dffe10a[17..0] : dffe;
	dffe5a[17..0] : dffe;
	dffe7a[17..0] : dffe;
	dffe8a[17..0] : dffe;
	dffe9a[17..0] : dffe;
	add_sub2 : add_sub_pc8;
	add_sub3 : add_sub_vt7;
	cntr1 : lpm_counter
		WITH (
			lpm_direction = "UP",
			lpm_width = 18
		);
	fast_feed_read	: WIRE;
	one[17..0]	: WIRE;
	read_count_actual[17..0]	: WIRE;
	w1w	: WIRE;
	w2w	: WIRE;

BEGIN 
	dpram4.aclr = aclr;
	dpram4.data[] = data[];
	dpram4.inclock = wrclk;
	dpram4.outclock = rdclk;
	dpram4.outclocken = w2w;
	dpram4.rdaddress[16..0] = read_count_actual[16..0];
	dpram4.wraddress[16..0] = cntr1.q[16..0];
	dpram4.wren = w1w;
	cs11a[].cin = ( ((! cs11a[0..0].cout) & wrreq), ((! (cntr1.q[17..17] $ dffe10a[17..17].Q)) $ add_sub2.cout));
	cs11a[].sin = ( ((! cs11a[0..0].cout) & wrreq), ((! (cntr1.q[17..17] $ dffe10a[17..17].Q)) $ add_sub2.cout));
	cs12a[].cin = ( ((! (cntr1.q[17..1] $ dffe10a[17..1].Q)) & cs12a[16..0].cout), (! (cntr1.q[0..0] $ dffe10a[0..0].Q)));
	cs12a[].sin = ( ((! (cntr1.q[17..1] $ dffe10a[17..1].Q)) & cs12a[16..0].cout), (! (cntr1.q[0..0] $ dffe10a[0..0].Q)));
	cs13a[].cin = ( ((! (dffe9a[17..1].Q $ dffe7a[17..1].Q)) & cs13a[16..0].cout), (! (dffe9a[0..0].Q $ dffe7a[0..0].Q)));
	cs13a[].sin = ( ((! (dffe9a[17..1].Q $ dffe7a[17..1].Q)) & cs13a[16..0].cout), (! (dffe9a[0..0].Q $ dffe7a[0..0].Q)));
	cs14.cin = ((! cs13a[17..17].cout) & rdreq);
	cs14.sin = ((! cs13a[17..17].cout) & rdreq);
	cs6a[].cin = ( (read_count_actual[17..1] & cs6a[16..0].cout), (fast_feed_read & read_count_actual[0..0]));
	cs6a[].sin = ( (read_count_actual[17..1] $ cs6a[16..0].cout), (fast_feed_read $ read_count_actual[0..0]));
	dffe10a[].CLK = wrclk;
	dffe10a[].CLRN = (! aclr);
	dffe10a[].D = dffe7a[].Q;
	dffe5a[].CLK = rdclk;
	dffe5a[].CLRN = (! aclr);
	dffe5a[].D = (cs6a[].sout $ one[]);
	dffe7a[].CLK = rdclk;
	dffe7a[].CLRN = (! aclr);
	dffe7a[].D = read_count_actual[];
	dffe7a[].ENA = w2w;
	dffe8a[].CLK = wrclk;
	dffe8a[].CLRN = (! aclr);
	dffe8a[].D = cntr1.q[];
	dffe9a[].CLK = rdclk;
	dffe9a[].CLRN = (! aclr);
	dffe9a[].D = dffe8a[].Q;
	add_sub2.dataa[16..0] = cntr1.q[16..0];
	add_sub2.datab[16..0] = dffe10a[16..0].Q;
	add_sub3.dataa[] = dffe9a[].Q;
	add_sub3.datab[] = dffe7a[].Q;
	cntr1.aclr = aclr;
	cntr1.clock = wrclk;
	cntr1.cnt_en = w1w;
	fast_feed_read = cs14.cout;
	one[] = B"000000000000000001";
	q[] = dpram4.q[];
	rdempty = cs13a[17..17].sout;
	rdfull = add_sub3.result[17..17];
	rdusedw[16..0] = add_sub3.result[16..0];
	read_count_actual[] = (dffe5a[].Q $ one[]);
	w1w = cs11a[1..1].sout;
	w2w = cs14.sout;
	wrempty = cs12a[17..17].sout;
	wrfull = cs11a[0..0].sout;
	wrusedw[16..0] = add_sub2.result[16..0];
END;
--VALID FILE