buffer422.tan.qmsg

一个同步422接口控制器的verilog源程序。

{ "Info" "ITDB_TSU_RESULT" "buff_control:inst\|data rst clk 6.912 ns register " "Info: tsu for register \"buff_control:inst\|data\" (data pin = \"rst\", clock pin = \"clk\") is 6.912 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.045 ns + Longest pin register " "Info: + Longest pin to register delay is 10.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_18 145 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_18; Fanout = 145; PIN Node = 'rst'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "buffer422.bdf" "" { Schematic "I:/work/buffer422/buffer422.bdf" { { 8 -136 32 24 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.709 ns) + CELL(0.867 ns) 10.045 ns buff_control:inst\|data 2 REG LC_X18_Y9_N4 32 " "Info: 2: + IC(7.709 ns) + CELL(0.867 ns) = 10.045 ns; Loc. = LC_X18_Y9_N4; Fanout = 32; REG Node = 'buff_control:inst\|data'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.576 ns" { rst buff_control:inst|data } "NODE_NAME" } } { "buff_control.v" "" { Text "I:/work/buffer422/buff_control.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 23.26 % ) " "Info: Total cell delay = 2.336 ns ( 23.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.709 ns ( 76.74 % ) " "Info: Total interconnect delay = 7.709 ns ( 76.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.045 ns" { rst buff_control:inst|data } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.045 ns" { rst rst~out0 buff_control:inst|data } { 0.000ns 0.000ns 7.709ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "buff_control.v" "" { Text "I:/work/buffer422/buff_control.v" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.170 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "buffer422.bdf" "" { Schematic "I:/work/buffer422/buffer422.bdf" { { 24 -136 32 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns buff_control:inst\|data 2 REG LC_X18_Y9_N4 32 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X18_Y9_N4; Fanout = 32; REG Node = 'buff_control:inst\|data'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clk buff_control:inst|data } "NODE_NAME" } } { "buff_control.v" "" { Text "I:/work/buffer422/buff_control.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk buff_control:inst|data } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 buff_control:inst|data } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.045 ns" { rst buff_control:inst|data } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.045 ns" { rst rst~out0 buff_control:inst|data } { 0.000ns 0.000ns 7.709ns } { 0.000ns 1.469ns 0.867ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk buff_control:inst|data } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 buff_control:inst|data } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_out buff_control:inst\|active 16.519 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_out\" through register \"buff_control:inst\|active\" is 16.519 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.669 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "buffer422.bdf" "" { Schematic "I:/work/buffer422/buffer422.bdf" { { 24 -136 32 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns buff_control:inst\|clkdiv 2 REG LC_X8_Y13_N9 439 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N9; Fanout = 439; REG Node = 'buff_control:inst\|clkdiv'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { clk buff_control:inst|clkdiv } "NODE_NAME" } } { "buff_control.v" "" { Text "I:/work/buffer422/buff_control.v" 126 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.523 ns) + CELL(0.711 ns) 7.669 ns buff_control:inst\|active 3 REG LC_X29_Y12_N4 8 " "Info: 3: + IC(3.523 ns) + CELL(0.711 ns) = 7.669 ns; Loc. = LC_X29_Y12_N4; Fanout = 8; REG Node = 'buff_control:inst\|active'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.234 ns" { buff_control:inst|clkdiv buff_control:inst|active } "NODE_NAME" } } { "buff_control.v" "" { Text "I:/work/buffer422/buff_control.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.62 % ) " "Info: Total cell delay = 3.115 ns ( 40.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.554 ns ( 59.38 % ) " "Info: Total interconnect delay = 4.554 ns ( 59.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.669 ns" { clk buff_control:inst|clkdiv buff_control:inst|active } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.669 ns" { clk clk~out0 buff_control:inst|clkdiv buff_control:inst|active } { 0.000ns 0.000ns 1.031