buffer422.tan.qmsg

一个同步422接口控制器的verilog源程序。

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register buff_control:inst\|data memory lpm_fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_so91:auto_generated\|alt_sync_fifo_fjm:sync_fifo\|dpram_evr:dpram4\|altsyncram_pof1:altsyncram14\|ram_block15a5~porta_datain_reg0 -2.609 ns " "Info: Minimum slack time is -2.609 ns for clock \"clk\" between source register \"buff_control:inst\|data\" and destination memory \"lpm_fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_so91:auto_generated\|alt_sync_fifo_fjm:sync_fifo\|dpram_evr:dpram4\|altsyncram_pof1:altsyncram14\|ram_block15a5~porta_datain_reg0\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.788 ns + Shortest register memory " "Info: + Shortest register to memory delay is 1.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buff_control:inst\|data 1 REG LC_X18_Y9_N4 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y9_N4; Fanout = 32; REG Node = 'buff_control:inst\|data'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { buff_control:inst|data } "NODE_NAME" } } { "buff_control.v" "" { Text "I:/work/buffer422/buff_control.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.432 ns) + CELL(0.356 ns) 1.788 ns lpm_fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_so91:auto_generated\|alt_sync_fifo_fjm:sync_fifo\|dpram_evr:dpram4\|altsyncram_pof1:altsyncram14\|ram_block15a5~porta_datain_reg0 2 MEM M4K_X19_Y9 1 " "Info: 2: + IC(1.432 ns) + CELL(0.356 ns) = 1.788 ns; Loc. = M4K_X19_Y9; Fanout = 1; MEM Node = 'lpm_fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_so91:auto_generated\|alt_sync_fifo_fjm:sync_fifo\|dpram_evr:dpram4\|altsyncram_pof1:altsyncram14\|ram_block15a5~porta_datain_reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.788 ns" { buff_control:inst|data lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_pof1.tdf" "" { Text "I:/work/buffer422/db/altsyncram_pof1.tdf" 206 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.356 ns ( 19.91 % ) " "Info: Total cell delay = 0.356 ns ( 19.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.432 ns ( 80.09 % ) " "Info: Total interconnect delay = 1.432 ns ( 80.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.788 ns" { buff_control:inst|data lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.788 ns" { buff_control:inst|data lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } { 0.000ns 1.432ns } { 0.000ns 0.356ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.397 ns - Smallest register memory " "Info: - Smallest register to memory requirement is 4.397 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 12.500 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 12.500 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 12.500 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 12.500 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.566 ns + Smallest " "Info: + Smallest clock skew is 4.566 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.736 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to destination memory is 7.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "buffer422.bdf" "" { Schematic "I:/work/buffer422/buffer422.bdf" { { 24 -136 32 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns buff_control:inst\|wrclk 2 REG LC_X8_Y13_N2 502 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N2; Fanout = 502; REG Node = 'buff_control:inst\|wrclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { clk buff_control:inst|wrclk } "NODE_NAME" } } { "buff_control.v" "" { Text "I:/work/buffer422/buff_control.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.579 ns) + CELL(0.722 ns) 7.736 ns lpm_fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_so91:auto_generated\|alt_sync_fifo_fjm:sync_fifo\|dpram_evr:dpram4\|altsyncram_pof1:altsyncram14\|ram_block15a5~porta_datain_reg0 3 MEM M4K_X19_Y9 1 " "Info: 3: + IC(3.579 ns) + CELL(0.722 ns) = 7.736 ns; Loc. = M4K_X19_Y9; Fanout = 1; MEM Node = 'lpm_fifo0:inst1\|dcfifo:dcfifo_component\|dcfifo_so91:auto_generated\|alt_sync_fifo_fjm:sync_fifo\|dpram_evr:dpram4\|altsyncram_pof1:altsyncram14\|ram_block15a5~porta_datain_reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.301 ns" { buff_control:inst|wrclk lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_pof1.tdf" "" { Text "I:/work/buffer422/db/altsyncram_pof1.tdf" 206 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.126 ns ( 40.41 % ) " "Info: Total cell delay = 3.126 ns ( 40.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.610 ns ( 59.59 % ) " "Info: Total interconnect delay = 4.610 ns ( 59.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.736 ns" { clk buff_control:inst|wrclk lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.736 ns" { clk clk~out0 buff_control:inst|wrclk lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } { 0.000ns 0.000ns 1.031ns 3.579ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.170 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "buffer422.bdf" "" { Schematic "I:/work/buffer422/buffer422.bdf" { { 24 -136 32 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns buff_control:inst\|data 2 REG LC_X18_Y9_N4 32 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X18_Y9_N4; Fanout = 32; REG Node = 'buff_control:inst\|data'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clk buff_control:inst|data } "NODE_NAME" } } { "buff_control.v" "" { Text "I:/work/buffer422/buff_control.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk buff_control:inst|data } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 buff_control:inst|data } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.736 ns" { clk buff_control:inst|wrclk lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.736 ns" { clk clk~out0 buff_control:inst|wrclk lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } { 0.000ns 0.000ns 1.031ns 3.579ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk buff_control:inst|data } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 buff_control:inst|data } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "buff_control.v" "" { Text "I:/work/buffer422/buff_control.v" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.055 ns + " "Info: + Micro hold delay of destination is 0.055 ns" {  } { { "db/altsyncram_pof1.tdf" "" { Text "I:/work/buffer422/db/altsyncram_pof1.tdf" 206 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.736 ns" { clk buff_control:inst|wrclk lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.736 ns" { clk clk~out0 buff_control:inst|wrclk lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } { 0.000ns 0.000ns 1.031ns 3.579ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk buff_control:inst|data } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 buff_control:inst|data } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.788 ns" { buff_control:inst|data lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.788 ns" { buff_control:inst|data lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } { 0.000ns 1.432ns } { 0.000ns 0.356ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.736 ns" { clk buff_control:inst|wrclk lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.736 ns" { clk clk~out0 buff_control:inst|wrclk lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0 } { 0.000ns 0.000ns 1.031ns 3.579ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk buff_control:inst|data } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 buff_control:inst|data } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "clk 17 " "Warning: Can't achieve minimum setup and hold requirement clk along 17 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}