📄 altsyncram_pof1.tdf
字号:
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 90111,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 86016,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 90111,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block15a22 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 90112,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 94207,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 90112,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 94207,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block15a23 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 94208,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 98303,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 94208,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 98303,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block15a24 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 98304,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 102399,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 98304,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 102399,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block15a25 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 102400,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 106495,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 102400,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 106495,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block15a26 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 106496,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 110591,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 106496,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 110591,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block15a27 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 110592,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 114687,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 110592,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 114687,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block15a28 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 114688,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 118783,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 114688,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 118783,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block15a29 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 118784,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 122879,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 118784,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 122879,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block15a30 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 122880,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 126975,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 122880,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 126975,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block15a31 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 126976,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 131071,
PORT_A_LOGICAL_RAM_DEPTH = 131072,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 126976,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 131071,
PORT_B_LOGICAL_RAM_DEPTH = 131072,
PORT_B_LOGICAL_RAM_WIDTH = 1,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
address_a_wire[16..0] : WIRE;
address_b_wire[16..0] : WIRE;
BEGIN
address_reg_b[].CLK = clock1;
address_reg_b[].D = address_b[16..12];
address_reg_b[].ENA = clocken1;
decode16.data[4..0] = address_a_wire[16..12];
decode16.enable = wren_a;
rden_decode.data[4..0] = address_b_wire[16..12];
rden_decode.enable = clocken1;
mux17.data[] = ( ram_block15a[31..0].portbdataout[0..0]);
mux17.sel[] = address_reg_b[].Q;
ram_block15a[31..0].clk0 = clock0;
ram_block15a[31..0].clk1 = clock1;
ram_block15a[31..0].ena0 = ( decode16.eq[31..0]);
ram_block15a[31..0].ena1 = ( rden_decode.eq[31..0]);
ram_block15a[31..0].portaaddr[] = ( address_a_wire[11..0]);
ram_block15a[31..0].portadatain[] = ( data_a[0..0]);
ram_block15a[31..0].portawe = B"11111111111111111111111111111111";
ram_block15a[31..0].portbaddr[] = ( address_b_wire[11..0]);
ram_block15a[31..0].portbrewe = B"11111111111111111111111111111111";
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_b[] = mux17.result[];
END;
--VALID FILE
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -