dpram_8vr.tdf

一个同步422接口控制器的verilog源程序。

--altdpram DEVICE_FAMILY="Cyclone" OUTDATA_REG="UNREGISTERED" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=1 WIDTHAD=11 data inclock outclock outclocken q rdaddress wraddress wren CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 6.0 cbx_altdpram 2006:01:09:10:52:42:SJ cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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FUNCTION altsyncram_dof1 (address_a[10..0], address_b[10..0], clock0, clock1, clocken1, data_a[0..0], wren_a)
RETURNS ( q_b[0..0]);

--synthesis_resources = M4K 16 
SUBDESIGN dpram_8vr
( 
	data[0..0]	:	input;
	inclock	:	input;
	outclock	:	input;
	outclocken	:	input;
	q[0..0]	:	output;
	rdaddress[10..0]	:	input;
	wraddress[10..0]	:	input;
	wren	:	input;
) 
VARIABLE 
	altsyncram14 : altsyncram_dof1;

BEGIN 
	altsyncram14.address_a[] = wraddress[];
	altsyncram14.address_b[] = rdaddress[];
	altsyncram14.clock0 = inclock;
	altsyncram14.clock1 = outclock;
	altsyncram14.clocken1 = outclocken;
	altsyncram14.data_a[] = data[];
	altsyncram14.wren_a = wren;
	q[] = altsyncram14.q_b[];
END;
--VALID FILE