📄 dcfifo_nbu.tdf
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--dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=32 CLOCKS_ARE_SYNCHRONIZED="TRUE" DEVICE_FAMILY="FLEX10K" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=131072 LPM_SHOWAHEAD="OFF" LPM_WIDTH=1 LPM_WIDTHU=17 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdreq rdusedw wrclk wrreq
--VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
-- Copyright (C) 1988-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION alt_sync_fifo_tfm (aclr, data[0..0], rdclk, rdreq, wrclk, wrreq)
RETURNS ( q[0..0], rdempty, rdfull, rdusedw[16..0], wrempty, wrfull, wrusedw[16..0]);
--synthesis_resources = altdpram 1 lpm_counter 1 lut 126
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
SUBDESIGN dcfifo_nbu
(
aclr : input;
data[0..0] : input;
q[0..0] : output;
rdclk : input;
rdempty : output;
rdfull : output;
rdreq : input;
rdusedw[16..0] : output;
wrclk : input;
wrempty : output;
wrfull : output;
wrreq : input;
wrusedw[16..0] : output;
)
VARIABLE
sync_fifo : alt_sync_fifo_tfm;
BEGIN
sync_fifo.aclr = aclr;
sync_fifo.data[] = data[];
sync_fifo.rdclk = rdclk;
sync_fifo.rdreq = rdreq;
sync_fifo.wrclk = wrclk;
sync_fifo.wrreq = wrreq;
q[] = sync_fifo.q[];
rdempty = sync_fifo.rdempty;
rdfull = sync_fifo.rdfull;
rdusedw[] = sync_fifo.rdusedw[];
wrempty = sync_fifo.wrempty;
wrfull = sync_fifo.wrfull;
wrusedw[] = sync_fifo.wrusedw[];
END;
--VALID FILE
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