buffer422.vwf

一个同步422接口控制器的verilog源程序。

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	PRINT_OPTIONS = "Print_options_version 6\
range_start 0ps\
range_end 10.0us\
width 1\
names_percentage 25\
comments 1\
grid_lines 1\
time_bars 1\
name_every_page 0\
expand_groups 0\
print_all 1";
	SIMULATION_TIME = 1000000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("clk_in")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("clk_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("data_in")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("data_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("rst")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("buff_control:inst|active")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("buff_control:inst|clcnt")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 3;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("buff_control:inst|clcnt[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "buff_control:inst|clcnt";
}

SIGNAL("buff_control:inst|clcnt[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "buff_control:inst|clcnt";
}

SIGNAL("buff_control:inst|clcnt[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "buff_control:inst|clcnt";
}

SIGNAL("buff_control:inst|clkdiv")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("buff_control:inst|cnt")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 5;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("buff_control:inst|cnt[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "buff_control:inst|cnt";
}

SIGNAL("buff_control:inst|cnt[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "buff_control:inst|cnt";
}

SIGNAL("buff_control:inst|cnt[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "buff_control:inst|cnt";
}

SIGNAL("buff_control:inst|cnt[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "buff_control:inst|cnt";
}

SIGNAL("buff_control:inst|cnt[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "buff_control:inst|cnt";
}

SIGNAL("buff_control:inst|d_active")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("buff_control:inst|dout")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("buff_control:inst|infoe_sel")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("buff_control:inst|infos_sel")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("rdreq")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 50000;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 10.0;
		}
	}
}

TRANSITION_LIST("clk_in")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 128;
			LEVEL 0 FOR 100.0;
			LEVEL 1 FOR 100.0;
		}
		LEVEL 0 FOR 8320.0;
		LEVEL 1 FOR 160.0;
		LEVEL 0 FOR 4220.0;
		LEVEL 1 FOR 100.0;
		NODE
		{
			REPEAT = 128;
			LEVEL 0 FOR 100.0;
			LEVEL 1 FOR 100.0;
		}
		LEVEL 0 FOR 26980.0;
		LEVEL 1 FOR 100.0;
		NODE
		{
			REPEAT = 5;
			LEVEL 0 FOR 100.0;
			LEVEL 1 FOR 100.0;
		}
		LEVEL 0 FOR 5220.0;
		LEVEL 1 FOR 100.0;
		NODE
		{
			REPEAT = 4513;
			LEVEL 0 FOR 100.0;
			LEVEL 1 FOR 100.0;
		}
	}
}

TRANSITION_LIST("clk_out")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 178.647;
		NODE
		{
			REPEAT = 4165;
			LEVEL 1 FOR 120.0;
			LEVEL 0 FOR 120.0;
		}
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 101.353;
	}
}

TRANSITION_LIST("data_in")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 400.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 600.0;
		LEVEL 1 FOR 200.0;
		NODE
		{
			REPEAT = 60;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 200.0;
		}
		LEVEL 0 FOR 8160.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 4000.0;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 200.0;
		NODE
		{
			REPEAT = 27;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 200.0;
		}
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 120.0;
		LEVEL 0 FOR 7880.0;
		LEVEL 1 FOR 200.0;
		NODE
		{
			REPEAT = 12;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 200.0;
		}
		LEVEL 0 FOR 400.0;
		LEVEL 1 FOR 400.0;
		LEVEL 0 FOR 27680.0;
		LEVEL 1 FOR 600.0;
		LEVEL 0 FOR 5520.0;
		LEVEL 1 FOR 600.0;
		LEVEL 0 FOR 600.0;
		LEVEL 1 FOR 200.0;
		NODE
		{
			REPEAT = 2253;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 200.0;
		}
	}
}

TRANSITION_LIST("data_out")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 250264.589;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 240.0;
		}
		LEVEL 1 FOR 1440.0;
		LEVEL 0 FOR 480.0;
		LEVEL 1 FOR 2400.0;
		LEVEL 0 FOR 1200.0;
		LEVEL 1 FOR 720.0;
		LEVEL 0 FOR 240.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 480.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 720.0;
		NODE
		{
			REPEAT = 60;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 240.0;
		}
		LEVEL 1 FOR 720.0;
		NODE
		{
			REPEAT = 29;
			LEVEL 0 FOR 240.0;
			LEVEL 1 FOR 240.0;
		}
		LEVEL 0 FOR 9360.0;
		NODE
		{
			REPEAT = 12;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 240.0;
		}
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 480.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 960.0;
		LEVEL 1 FOR 720.0;
		LEVEL 0 FOR 480.0;
		LEVEL 1 FOR 720.0;
		LEVEL 0 FOR 720.0;
		NODE
		{
			REPEAT = 1410;
			LEVEL 1 FOR 240.0;
			LEVEL 0 FOR 240.0;
		}
		LEVEL 1 FOR 215.411;
	}
}

TRANSITION_LIST("rst")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 999940.0;
	}
}

TRANSITION_LIST("buff_control:inst|active")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 249777.893;
		LEVEL 1 FOR 750222.107;