buff_control.v

一个同步422接口控制器的verilog源程序。

module buff_control(
	rst,
	clk, 
	tdin,
	rdusedw,
	data_in,
	clk_in, 
	aclr,
	rdreq,
	dout,
	clout,
	rdclk,
	data,
	wrclk
);

	//
	// inputs & outputs
	//
	input rst;					// systen reset
	input clk;					// system clock				
	input tdin;					// fifo data out
	input [16:0] rdusedw;		// fifo words number
	input data_in;				// 422 data in
	input clk_in;				// 422 synchronous clk in
	output aclr;				// fifo asynchronous clear
	output rdreq;				// fifo read require
	output dout;                // 422 data out
	output clout; 				// 422 synchronous clk out
	output rdclk;				// fifo read clk
	output wrclk;				// fifo write clk
	output data;				// fifo data in

	//
	// variables
	//
	reg fos,foe;
	reg dfos,dfoe;
	reg active;
	reg d_active,dd_active;
	reg infos_sel,infoe_sel;
	reg [4:0] cnt;
	reg clkdiv;
	reg dout;
	wire clout;
	wire rdclk;
	reg [2 :0] clcnt;
	reg [31:0] infos,infoe;
	reg rdreq;
	wire aclr;
	reg wrclk,data;
	reg clk_reg,clk_reg1,clk_reg2,clk_reg3;
	reg dat_reg,dat_reg1,dat_reg2,dat_reg3;
	reg clen;
	reg [27:0] dly_cnt;
	//
	// module body
	//
	
	always@(posedge clk or negedge rst)
		if (~rst)
		begin
			clk_reg <= 1'b0;
			clk_reg1 <= 1'b0;
			clk_reg2 <= 1'b0;
			clk_reg3 <= 1'b0;
			
			dat_reg <= 1'b0;
			dat_reg1 <= 1'b0;
			dat_reg2 <= 1'b0;
			dat_reg3 <= 1'b0;
		end
		else
		begin
			clk_reg <= clk_in;
			clk_reg1 <= clk_reg;
			clk_reg2 <= clk_reg1;
			clk_reg3 <= clk_reg2;
			wrclk <= clk_reg3;
			
			dat_reg <= data_in;
			dat_reg1 <= dat_reg;
			dat_reg2 <= dat_reg1;
			dat_reg3 <= dat_reg2;
			data <= dat_reg3;
		end
		
	always@(posedge clk or negedge rst)
		if (~rst)
			clcnt <= 3'b0;
		else
			if (clcnt < 3'b101)
				clcnt <= clcnt + 3'b1;
			else
				clcnt <= 3'b0;
	
	always@(posedge clk or negedge rst)
		if (~rst)
			clen <= 1'b0;
		else
			if ((~active)&d_active)
				clen <= 1'b1;
			else if((dly_cnt==28'hFFFFFFF)|active)
				clen <= 1'b0;
				
	always@(posedge clk or negedge rst)
		if (~rst)
			dly_cnt <= 28'h0;
		else
			if (clen)
				begin
					if (dly_cnt < 28'hFFFFFFF)
						dly_cnt <= dly_cnt + 28'h1;
					else
						dly_cnt <= 28'h0;
				end
			else
				dly_cnt <= 28'h0;
						
	assign clout = clkdiv & (clen|active|dd_active);
	assign rdclk = clkdiv;
				
	always@(posedge clk or negedge rst)
		if (~rst)
			clkdiv <= 1'b0;
		else
			if (clcnt==3'b101)
				clkdiv <= ~clkdiv;

	always@(posedge clkdiv or negedge rst)
		if (~rst)
			rdreq <= 1'b0;
		else
			if (cnt == 5'h1e & infos_sel)
				rdreq <= 1'b1;
			else
				if (rdusedw==6'b1)
					rdreq <= 1'b0;
		
	always@(posedge clkdiv or negedge rst)
		if (~rst)
			active <= 1'b0;
		else
			if (rdusedw==6'b1)
				active <= 1'b0;
			else
				if (rdusedw[16])
					active <= 1'b1;
					
	always@(posedge clkdiv or negedge rst)
		if (~rst)
		begin			
			d_active <= 1'b0;
			dd_active <= 1'b0;
		end
		else
		begin
			d_active <= active;
			dd_active <= d_active;
		end

	
	always@(posedge clkdiv or negedge rst)
		if(~rst)
			infos_sel <= 1'b0;
		else
			if (active&(~d_active))
				infos_sel <= 1'b1;
			else
				if (&cnt)
					infos_sel <= 1'b0;
	
	assign aclr =  ~rst;
					
	always@(posedge clkdiv or negedge rst)
		if(~rst)
			infoe_sel <= 1'b0;
		else
			if (dd_active&(~d_active))
				infoe_sel <= 1'b1;
			else
				if (&cnt)
					infoe_sel <= 1'b0;
	
	always@(posedge clkdiv or negedge rst)
		if (~rst)
			cnt <= 5'b00000;
		else
			if (infos_sel | infoe_sel)
				if (~(&cnt))
					cnt <= cnt + 5'b00001;
				else
					cnt <= 5'b00000;
										
	always@(posedge clkdiv or negedge rst)
		if (~rst)
			infos <= 32'hffff_fc1d;
		else
			infos <= 32'hffff_fc1d;
	
	always@(posedge clkdiv or negedge rst)
		if (~rst)
			infoe <= 32'hffff_1acf;
		else
			infoe <= 32'hffff_1acf;
	

	always@(posedge clkdiv or negedge rst)
		if (~rst)
			dout <= 1'b0;
		else
			if (infos_sel)
				dout <= infos[31-cnt];
			else
				if (infoe_sel)
					dout <= infoe[31-cnt];
				else
					if (active)
						dout <= tdin;
					else
						dout <= 1'b0;			
					
endmodule