buffer422.tan.rpt

一个同步422接口控制器的verilog源程序。

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                     ; To                                                                                                                                                                             ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A       ; None                             ; 6.912 ns                         ; rst                                                                                                      ; buff_control:inst|data                                                                                                                                                         ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A       ; None                             ; 16.519 ns                        ; buff_control:inst|active                                                                                 ; clk_out                                                                                                                                                                        ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A       ; None                             ; -5.168 ns                        ; clk_in                                                                                                   ; buff_control:inst|clk_reg                                                                                                                                                      ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; 1.169 ns  ; 80.00 MHz ( period = 12.500 ns ) ; 88.25 MHz ( period = 11.331 ns ) ; lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dffe9a[9] ; lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a6~porta_address_reg11 ; clk        ; clk      ; 0            ;
; Clock Hold: 'clk'            ; -2.609 ns ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; buff_control:inst|data                                                                                   ; lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_so91:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_evr:dpram4|altsyncram_pof1:altsyncram14|ram_block15a5~porta_datain_reg0   ; clk        ; clk      ; 17           ;
; Total number of failed paths ;           ;                                  ;                                  ;                                                                                                          ;                                                                                                                                                                                ;            ;          ; 17           ;
+------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 80 MHz             ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+