buffer422.fit.eqn

一个同步422接口控制器的verilog源程序。

--L1_address_reg_b[4] is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|address_reg_b[4] at LC_X22_Y14_N9
--operation mode is normal

L1_address_reg_b[4] = DFFEAS(B1L13, GLOBAL(B1_clkdiv), VCC, , F1_w2w, F1_dffe5a[16], , , VCC);


--L1_ram_block15a18 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a18 at M4K_X33_Y19
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a18_PORT_A_data_in = data_in;
L1_ram_block15a18_PORT_A_data_in_reg = DFFE(L1_ram_block15a18_PORT_A_data_in, L1_ram_block15a18_clock_0, , , L1_ram_block15a18_clock_enable_0);
L1_ram_block15a18_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a18_PORT_A_address_reg = DFFE(L1_ram_block15a18_PORT_A_address, L1_ram_block15a18_clock_0, , , L1_ram_block15a18_clock_enable_0);
L1_ram_block15a18_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a18_PORT_B_address_reg = DFFE(L1_ram_block15a18_PORT_B_address, L1_ram_block15a18_clock_1, , , L1_ram_block15a18_clock_enable_1);
L1_ram_block15a18_PORT_A_write_enable = VCC;
L1_ram_block15a18_PORT_A_write_enable_reg = DFFE(L1_ram_block15a18_PORT_A_write_enable, L1_ram_block15a18_clock_0, , , L1_ram_block15a18_clock_enable_0);
L1_ram_block15a18_PORT_B_read_enable = VCC;
L1_ram_block15a18_PORT_B_read_enable_reg = DFFE(L1_ram_block15a18_PORT_B_read_enable, L1_ram_block15a18_clock_1, , , L1_ram_block15a18_clock_enable_1);
L1_ram_block15a18_clock_0 = GLOBAL(clk_in);
L1_ram_block15a18_clock_1 = GLOBAL(B1_clkdiv);
L1_ram_block15a18_clock_enable_0 = M1_w_anode595w[3];
L1_ram_block15a18_clock_enable_1 = F1_w2w;
L1_ram_block15a18_PORT_B_data_out = MEMORY(L1_ram_block15a18_PORT_A_data_in_reg, , L1_ram_block15a18_PORT_A_address_reg, L1_ram_block15a18_PORT_B_address_reg, L1_ram_block15a18_PORT_A_write_enable_reg, L1_ram_block15a18_PORT_B_read_enable_reg, , , L1_ram_block15a18_clock_0, L1_ram_block15a18_clock_1, L1_ram_block15a18_clock_enable_0, L1_ram_block15a18_clock_enable_1, , );
L1_ram_block15a18 = L1_ram_block15a18_PORT_B_data_out[0];


--L1_ram_block15a17 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a17 at M4K_X19_Y6
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a17_PORT_A_data_in = data_in;
L1_ram_block15a17_PORT_A_data_in_reg = DFFE(L1_ram_block15a17_PORT_A_data_in, L1_ram_block15a17_clock_0, , , L1_ram_block15a17_clock_enable_0);
L1_ram_block15a17_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a17_PORT_A_address_reg = DFFE(L1_ram_block15a17_PORT_A_address, L1_ram_block15a17_clock_0, , , L1_ram_block15a17_clock_enable_0);
L1_ram_block15a17_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a17_PORT_B_address_reg = DFFE(L1_ram_block15a17_PORT_B_address, L1_ram_block15a17_clock_1, , , L1_ram_block15a17_clock_enable_1);
L1_ram_block15a17_PORT_A_write_enable = VCC;
L1_ram_block15a17_PORT_A_write_enable_reg = DFFE(L1_ram_block15a17_PORT_A_write_enable, L1_ram_block15a17_clock_0, , , L1_ram_block15a17_clock_enable_0);
L1_ram_block15a17_PORT_B_read_enable = VCC;
L1_ram_block15a17_PORT_B_read_enable_reg = DFFE(L1_ram_block15a17_PORT_B_read_enable, L1_ram_block15a17_clock_1, , , L1_ram_block15a17_clock_enable_1);
L1_ram_block15a17_clock_0 = GLOBAL(clk_in);
L1_ram_block15a17_clock_1 = GLOBAL(B1_clkdiv);
L1_ram_block15a17_clock_enable_0 = M1_w_anode585w[3];
L1_ram_block15a17_clock_enable_1 = F1_w2w;
L1_ram_block15a17_PORT_B_data_out = MEMORY(L1_ram_block15a17_PORT_A_data_in_reg, , L1_ram_block15a17_PORT_A_address_reg, L1_ram_block15a17_PORT_B_address_reg, L1_ram_block15a17_PORT_A_write_enable_reg, L1_ram_block15a17_PORT_B_read_enable_reg, , , L1_ram_block15a17_clock_0, L1_ram_block15a17_clock_1, L1_ram_block15a17_clock_enable_0, L1_ram_block15a17_clock_enable_1, , );
L1_ram_block15a17 = L1_ram_block15a17_PORT_B_data_out[0];


--L1_ram_block15a16 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a16 at M4K_X19_Y11
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a16_PORT_A_data_in = data_in;
L1_ram_block15a16_PORT_A_data_in_reg = DFFE(L1_ram_block15a16_PORT_A_data_in, L1_ram_block15a16_clock_0, , , L1_ram_block15a16_clock_enable_0);
L1_ram_block15a16_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a16_PORT_A_address_reg = DFFE(L1_ram_block15a16_PORT_A_address, L1_ram_block15a16_clock_0, , , L1_ram_block15a16_clock_enable_0);
L1_ram_block15a16_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a16_PORT_B_address_reg = DFFE(L1_ram_block15a16_PORT_B_address, L1_ram_block15a16_clock_1, , , L1_ram_block15a16_clock_enable_1);
L1_ram_block15a16_PORT_A_write_enable = VCC;
L1_ram_block15a16_PORT_A_write_enable_reg = DFFE(L1_ram_block15a16_PORT_A_write_enable, L1_ram_block15a16_clock_0, , , L1_ram_block15a16_clock_enable_0);
L1_ram_block15a16_PORT_B_read_enable = VCC;
L1_ram_block15a16_PORT_B_read_enable_reg = DFFE(L1_ram_block15a16_PORT_B_read_enable, L1_ram_block15a16_clock_1, , , L1_ram_block15a16_clock_enable_1);
L1_ram_block15a16_clock_0 = GLOBAL(clk_in);
L1_ram_block15a16_clock_1 = GLOBAL(B1_clkdiv);
L1_ram_block15a16_clock_enable_0 = M1_w_anode574w[3];
L1_ram_block15a16_clock_enable_1 = F1_w2w;
L1_ram_block15a16_PORT_B_data_out = MEMORY(L1_ram_block15a16_PORT_A_data_in_reg, , L1_ram_block15a16_PORT_A_address_reg, L1_ram_block15a16_PORT_B_address_reg, L1_ram_block15a16_PORT_A_write_enable_reg, L1_ram_block15a16_PORT_B_read_enable_reg, , , L1_ram_block15a16_clock_0, L1_ram_block15a16_clock_1, L1_ram_block15a16_clock_enable_0, L1_ram_block15a16_clock_enable_1, , );
L1_ram_block15a16 = L1_ram_block15a16_PORT_B_data_out[0];


--N1L51 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|mux_6o7:mux17|w_result1055w~445 at LC_X21_Y14_N5
--operation mode is normal

L1_address_reg_b[1]_qfbk = L1_address_reg_b[1];
N1L51 = L1_address_reg_b[0] & (L1_ram_block15a17 # L1_address_reg_b[1]_qfbk) # !L1_address_reg_b[0] & (!L1_address_reg_b[1]_qfbk & L1_ram_block15a16);

--L1_address_reg_b[1] is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|address_reg_b[1] at LC_X21_Y14_N5
--operation mode is normal

L1_address_reg_b[1] = DFFEAS(N1L51, GLOBAL(B1_clkdiv), VCC, , F1_w2w, F1_dffe5a[13], , , VCC);


--L1_ram_block15a19 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a19 at M4K_X19_Y8
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a19_PORT_A_data_in = data_in;
L1_ram_block15a19_PORT_A_data_in_reg = DFFE(L1_ram_block15a19_PORT_A_data_in, L1_ram_block15a19_clock_0, , , L1_ram_block15a19_clock_enable_0);
L1_ram_block15a19_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a19_PORT_A_address_reg = DFFE(L1_ram_block15a19_PORT_A_address, L1_ram_block15a19_clock_0, , , L1_ram_block15a19_clock_enable_0);
L1_ram_block15a19_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a19_PORT_B_address_reg = DFFE(L1_ram_block15a19_PORT_B_address, L1_ram_block15a19_clock_1, , , L1_ram_block15a19_clock_enable_1);
L1_ram_block15a19_PORT_A_write_enable = VCC;
L1_ram_block15a19_PORT_A_write_enable_reg = DFFE(L1_ram_block15a19_PORT_A_write_enable, L1_ram_block15a19_clock_0, , , L1_ram_block15a19_clock_enable_0);
L1_ram_block15a19_PORT_B_read_enable = VCC;
L1_ram_block15a19_PORT_B_read_enable_reg = DFFE(L1_ram_block15a19_PORT_B_read_enable, L1_ram_block15a19_clock_1, , , L1_ram_block15a19_clock_enable_1);
L1_ram_block15a19_clock_0 = GLOBAL(clk_in);
L1_ram_block15a19_clock_1 = GLOBAL(B1_clkdiv);
L1_ram_block15a19_clock_enable_0 = M1_w_anode605w[3];
L1_ram_block15a19_clock_enable_1 = F1_w2w;
L1_ram_block15a19_PORT_B_data_out = MEMORY(L1_ram_block15a19_PORT_A_data_in_reg, , L1_ram_block15a19_PORT_A_address_reg, L1_ram_block15a19_PORT_B_address_reg, L1_ram_block15a19_PORT_A_write_enable_reg, L1_ram_block15a19_PORT_B_read_enable_reg, , , L1_ram_block15a19_clock_0, L1_ram_block15a19_clock_1, L1_ram_block15a19_clock_enable_0, L1_ram_block15a19_clock_enable_1, , );
L1_ram_block15a19 = L1_ram_block15a19_PORT_B_data_out[0];


--N1L61 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|mux_6o7:mux17|w_result1055w~446 at LC_X21_Y14_N1
--operation mode is normal

N1L61 = L1_address_reg_b[1] & (N1L51 & (L1_ram_block15a19) # !N1L51 & L1_ram_block15a18) # !L1_address_reg_b[1] & (N1L51);


--N1L71 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|mux_6o7:mux17|w_result1055w~447 at LC_X21_Y14_N8
--operation mode is normal

L1_address_reg_b[3]_qfbk = L1_address_reg_b[3];
N1L71 = !L1_address_reg_b[2] & !L1_address_reg_b[3]_qfbk & N1L61;

--L1_address_reg_b[3] is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|address_reg_b[3] at LC_X21_Y14_N8
--operation mode is normal

L1_address_reg_b[3] = DFFEAS(N1L71, GLOBAL(B1_clkdiv), VCC, , F1_w2w, F1_dffe5a[15], , , VCC);


--L1_ram_block15a27 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a27 at M4K_X19_Y5
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a27_PORT_A_data_in = data_in;
L1_ram_block15a27_PORT_A_data_in_reg = DFFE(L1_ram_block15a27_PORT_A_data_in, L1_ram_block15a27_clock_0, , , L1_ram_block15a27_clock_enable_0);
L1_ram_block15a27_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a27_PORT_A_address_reg = DFFE(L1_ram_block15a27_PORT_A_address, L1_ram_block15a27_clock_0, , , L1_ram_block15a27_clock_enable_0);
L1_ram_block15a27_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a27_PORT_B_address_reg = DFFE(L1_ram_block15a27_PORT_B_address, L1_ram_block15a27_clock_1, , , L1_ram_block15a27_clock_enable_1);
L1_ram_block15a27_PORT_A_write_enable = VCC;
L1_ram_block15a27_PORT_A_write_enable_reg = DFFE(L1_ram_block15a27_PORT_A_write_enable, L1_ram_block15a27_clock_0, , , L1_ram_block15a27_clock_enable_0);
L1_ram_block15a27_PORT_B_read_enable = VCC;
L1_ram_block15a27_PORT_B_read_enable_reg = DFFE(L1_ram_block15a27_PORT_B_read_enable, L1_ram_block15a27_clock_1, , , L1_ram_block15a27_clock_enable_1);
L1_ram_block15a27_clock_0 = GLOBAL(clk_in);
L1_ram_block15a27_clock_1 = GLOBAL(B1_clkdiv);
L1_ram_block15a27_clock_enable_0 = M1_w_anode696w[3];
L1_ram_block15a27_clock_enable_1 = F1_w2w;
L1_ram_block15a27_PORT_B_data_out = MEMORY(L1_ram_block15a27_PORT_A_data_in_reg, , L1_ram_block15a27_PORT_A_address_reg, L1_ram_block15a27_PORT_B_address_reg, L1_ram_block15a27_PORT_A_write_enable_reg, L1_ram_block15a27_PORT_B_read_enable_reg, , , L1_ram_block15a27_clock_0, L1_ram_block15a27_clock_1, L1_ram_block15a27_clock_enable_0, L1_ram_block15a27_clock_enable_1, , );
L1_ram_block15a27 = L1_ram_block15a27_PORT_B_data_out[0];


--L1_ram_block15a25 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a25 at M4K_X19_Y9
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a25_PORT_A_data_in = data_in;
L1_ram_block15a25_PORT_A_data_in_reg = DFFE(L1_ram_block15a25_PORT_A_data_in, L1_ram_block15a25_clock_0, , , L1_ram_block15a25_clock_enable_0);
L1_ram_block15a25_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a25_PORT_A_address_reg = DFFE(L1_ram_block15a25_PORT_A_address, L1_ram_block15a25_clock_0, , , L1_ram_block15a25_clock_enable_0);
L1_ram_block15a25_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a25_PORT_B_address_reg = DFFE(L1_ram_block15a25_PORT_B_address, L1_ram_block15a25_clock_1, , , L1_ram_block15a25_clock_enable_1);
L1_ram_block15a25_PORT_A_write_enable = VCC;
L1_ram_block15a25_PORT_A_write_enable_reg = DFFE(L1_ram_block15a25_PORT_A_write_enable, L1_ram_block15a25_clock_0, , , L1_ram_block15a25_clock_enable_0);
L1_ram_block15a25_PORT_B_read_enable = VCC;
L1_ram_block15a25_PORT_B_read_enable_reg = DFFE(L1_ram_block15a25_PORT_B_read_enable, L1_ram_block15a25_clock_1, , , L1_ram_block15a25_clock_enable_1);
L1_ram_block15a25_clock_0 = GLOBAL(clk_in);
L1_ram_block15a25_clock_1 = GLOBAL(B1_clkdiv);
L1_ram_block15a25_clock_enable_0 = M1_w_anode676w[3];
L1_ram_block15a25_clock_enable_1 = F1_w2w;
L1_ram_b