buffer422.map.eqn

一个同步422接口控制器的verilog源程序。

--B1L62 is buff_control:inst|dout~441
--operation mode is normal

B1L62 = L1_address_reg_b[2] & B1_active & B1L52 & !L1_address_reg_b[3];


--L1_ram_block15a29 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a29
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a29_PORT_A_data_in = data_in;
L1_ram_block15a29_PORT_A_data_in_reg = DFFE(L1_ram_block15a29_PORT_A_data_in, L1_ram_block15a29_clock_0, , , L1_ram_block15a29_clock_enable_0);
L1_ram_block15a29_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a29_PORT_A_address_reg = DFFE(L1_ram_block15a29_PORT_A_address, L1_ram_block15a29_clock_0, , , L1_ram_block15a29_clock_enable_0);
L1_ram_block15a29_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a29_PORT_B_address_reg = DFFE(L1_ram_block15a29_PORT_B_address, L1_ram_block15a29_clock_1, , , L1_ram_block15a29_clock_enable_1);
L1_ram_block15a29_PORT_A_write_enable = VCC;
L1_ram_block15a29_PORT_A_write_enable_reg = DFFE(L1_ram_block15a29_PORT_A_write_enable, L1_ram_block15a29_clock_0, , , L1_ram_block15a29_clock_enable_0);
L1_ram_block15a29_PORT_B_read_enable = VCC;
L1_ram_block15a29_PORT_B_read_enable_reg = DFFE(L1_ram_block15a29_PORT_B_read_enable, L1_ram_block15a29_clock_1, , , L1_ram_block15a29_clock_enable_1);
L1_ram_block15a29_clock_0 = clk_in;
L1_ram_block15a29_clock_1 = B1_clkdiv;
L1_ram_block15a29_clock_enable_0 = M1_w_anode716w[3];
L1_ram_block15a29_clock_enable_1 = F1_w2w;
L1_ram_block15a29_PORT_B_data_out = MEMORY(L1_ram_block15a29_PORT_A_data_in_reg, , L1_ram_block15a29_PORT_A_address_reg, L1_ram_block15a29_PORT_B_address_reg, L1_ram_block15a29_PORT_A_write_enable_reg, L1_ram_block15a29_PORT_B_read_enable_reg, , , L1_ram_block15a29_clock_0, L1_ram_block15a29_clock_1, L1_ram_block15a29_clock_enable_0, L1_ram_block15a29_clock_enable_1, , );
L1_ram_block15a29 = L1_ram_block15a29_PORT_B_data_out[0];


--L1_ram_block15a30 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a30
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a30_PORT_A_data_in = data_in;
L1_ram_block15a30_PORT_A_data_in_reg = DFFE(L1_ram_block15a30_PORT_A_data_in, L1_ram_block15a30_clock_0, , , L1_ram_block15a30_clock_enable_0);
L1_ram_block15a30_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a30_PORT_A_address_reg = DFFE(L1_ram_block15a30_PORT_A_address, L1_ram_block15a30_clock_0, , , L1_ram_block15a30_clock_enable_0);
L1_ram_block15a30_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a30_PORT_B_address_reg = DFFE(L1_ram_block15a30_PORT_B_address, L1_ram_block15a30_clock_1, , , L1_ram_block15a30_clock_enable_1);
L1_ram_block15a30_PORT_A_write_enable = VCC;
L1_ram_block15a30_PORT_A_write_enable_reg = DFFE(L1_ram_block15a30_PORT_A_write_enable, L1_ram_block15a30_clock_0, , , L1_ram_block15a30_clock_enable_0);
L1_ram_block15a30_PORT_B_read_enable = VCC;
L1_ram_block15a30_PORT_B_read_enable_reg = DFFE(L1_ram_block15a30_PORT_B_read_enable, L1_ram_block15a30_clock_1, , , L1_ram_block15a30_clock_enable_1);
L1_ram_block15a30_clock_0 = clk_in;
L1_ram_block15a30_clock_1 = B1_clkdiv;
L1_ram_block15a30_clock_enable_0 = M1_w_anode726w[3];
L1_ram_block15a30_clock_enable_1 = F1_w2w;
L1_ram_block15a30_PORT_B_data_out = MEMORY(L1_ram_block15a30_PORT_A_data_in_reg, , L1_ram_block15a30_PORT_A_address_reg, L1_ram_block15a30_PORT_B_address_reg, L1_ram_block15a30_PORT_A_write_enable_reg, L1_ram_block15a30_PORT_B_read_enable_reg, , , L1_ram_block15a30_clock_0, L1_ram_block15a30_clock_1, L1_ram_block15a30_clock_enable_0, L1_ram_block15a30_clock_enable_1, , );
L1_ram_block15a30 = L1_ram_block15a30_PORT_B_data_out[0];


--L1_ram_block15a28 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a28
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a28_PORT_A_data_in = data_in;
L1_ram_block15a28_PORT_A_data_in_reg = DFFE(L1_ram_block15a28_PORT_A_data_in, L1_ram_block15a28_clock_0, , , L1_ram_block15a28_clock_enable_0);
L1_ram_block15a28_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a28_PORT_A_address_reg = DFFE(L1_ram_block15a28_PORT_A_address, L1_ram_block15a28_clock_0, , , L1_ram_block15a28_clock_enable_0);
L1_ram_block15a28_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a28_PORT_B_address_reg = DFFE(L1_ram_block15a28_PORT_B_address, L1_ram_block15a28_clock_1, , , L1_ram_block15a28_clock_enable_1);
L1_ram_block15a28_PORT_A_write_enable = VCC;
L1_ram_block15a28_PORT_A_write_enable_reg = DFFE(L1_ram_block15a28_PORT_A_write_enable, L1_ram_block15a28_clock_0, , , L1_ram_block15a28_clock_enable_0);
L1_ram_block15a28_PORT_B_read_enable = VCC;
L1_ram_block15a28_PORT_B_read_enable_reg = DFFE(L1_ram_block15a28_PORT_B_read_enable, L1_ram_block15a28_clock_1, , , L1_ram_block15a28_clock_enable_1);
L1_ram_block15a28_clock_0 = clk_in;
L1_ram_block15a28_clock_1 = B1_clkdiv;
L1_ram_block15a28_clock_enable_0 = M1_w_anode706w[3];
L1_ram_block15a28_clock_enable_1 = F1_w2w;
L1_ram_block15a28_PORT_B_data_out = MEMORY(L1_ram_block15a28_PORT_A_data_in_reg, , L1_ram_block15a28_PORT_A_address_reg, L1_ram_block15a28_PORT_B_address_reg, L1_ram_block15a28_PORT_A_write_enable_reg, L1_ram_block15a28_PORT_B_read_enable_reg, , , L1_ram_block15a28_clock_0, L1_ram_block15a28_clock_1, L1_ram_block15a28_clock_enable_0, L1_ram_block15a28_clock_enable_1, , );
L1_ram_block15a28 = L1_ram_block15a28_PORT_B_data_out[0];


--N1L31 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|mux_6o7:mux17|w_result1038w~49
--operation mode is normal

N1L31 = L1_address_reg_b[0] & (L1_address_reg_b[1]) # !L1_address_reg_b[0] & (L1_address_reg_b[1] & L1_ram_block15a30 # !L1_address_reg_b[1] & (L1_ram_block15a28));


--L1_ram_block15a31 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a31
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a31_PORT_A_data_in = data_in;
L1_ram_block15a31_PORT_A_data_in_reg = DFFE(L1_ram_block15a31_PORT_A_data_in, L1_ram_block15a31_clock_0, , , L1_ram_block15a31_clock_enable_0);
L1_ram_block15a31_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a31_PORT_A_address_reg = DFFE(L1_ram_block15a31_PORT_A_address, L1_ram_block15a31_clock_0, , , L1_ram_block15a31_clock_enable_0);
L1_ram_block15a31_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a31_PORT_B_address_reg = DFFE(L1_ram_block15a31_PORT_B_address, L1_ram_block15a31_clock_1, , , L1_ram_block15a31_clock_enable_1);
L1_ram_block15a31_PORT_A_write_enable = VCC;
L1_ram_block15a31_PORT_A_write_enable_reg = DFFE(L1_ram_block15a31_PORT_A_write_enable, L1_ram_block15a31_clock_0, , , L1_ram_block15a31_clock_enable_0);
L1_ram_block15a31_PORT_B_read_enable = VCC;
L1_ram_block15a31_PORT_B_read_enable_reg = DFFE(L1_ram_block15a31_PORT_B_read_enable, L1_ram_block15a31_clock_1, , , L1_ram_block15a31_clock_enable_1);
L1_ram_block15a31_clock_0 = clk_in;
L1_ram_block15a31_clock_1 = B1_clkdiv;
L1_ram_block15a31_clock_enable_0 = M1_w_anode736w[3];
L1_ram_block15a31_clock_enable_1 = F1_w2w;
L1_ram_block15a31_PORT_B_data_out = MEMORY(L1_ram_block15a31_PORT_A_data_in_reg, , L1_ram_block15a31_PORT_A_address_reg, L1_ram_block15a31_PORT_B_address_reg, L1_ram_block15a31_PORT_A_write_enable_reg, L1_ram_block15a31_PORT_B_read_enable_reg, , , L1_ram_block15a31_clock_0, L1_ram_block15a31_clock_1, L1_ram_block15a31_clock_enable_0, L1_ram_block15a31_clock_enable_1, , );
L1_ram_block15a31 = L1_ram_block15a31_PORT_B_data_out[0];


--N1L41 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|mux_6o7:mux17|w_result1038w~50
--operation mode is normal

N1L41 = L1_address_reg_b[0] & (N1L31 & (L1_ram_block15a31) # !N1L31 & L1_ram_block15a29) # !L1_address_reg_b[0] & (N1L31);


--B1L72 is buff_control:inst|dout~442
--operation mode is normal

B1L72 = B1_active & L1_address_reg_b[4] & (N1L41 # !L1_address_reg_b[2]);


--L1_ram_block15a18 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a18
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a18_PORT_A_data_in = data_in;
L1_ram_block15a18_PORT_A_data_in_reg = DFFE(L1_ram_block15a18_PORT_A_data_in, L1_ram_block15a18_clock_0, , , L1_ram_block15a18_clock_enable_0);
L1_ram_block15a18_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a18_PORT_A_address_reg = DFFE(L1_ram_block15a18_PORT_A_address, L1_ram_block15a18_clock_0, , , L1_ram_block15a18_clock_enable_0);
L1_ram_block15a18_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a18_PORT_B_address_reg = DFFE(L1_ram_block15a18_PORT_B_address, L1_ram_block15a18_clock_1, , , L1_ram_block15a18_clock_enable_1);
L1_ram_block15a18_PORT_A_write_enable = VCC;
L1_ram_block15a18_PORT_A_write_enable_reg = DFFE(L1_ram_block15a18_PORT_A_write_enable, L1_ram_block15a18_clock_0, , , L1_ram_block15a18_clock_enable_0);
L1_ram_block15a18_PORT_B_read_enable = VCC;
L1_ram_block15a18_PORT_B_read_enable_reg = DFFE(L1_ram_block15a18_PORT_B_read_enable, L1_ram_block15a18_clock_1, , , L1_ram_block15a18_clock_enable_1);
L1_ram_block15a18_clock_0 = clk_in;
L1_ram_block15a18_clock_1 = B1_clkdiv;
L1_ram_block15a18_clock_enable_0 = M1_w_anode595w[3];
L1_ram_block15a18_clock_enable_1 = F1_w2w;
L1_ram_block15a18_PORT_B_data_out = MEMORY(L1_ram_block15a18_PORT_A_data_in_reg, , L1_ram_block15a18_PORT_A_address_reg, L1_ram_block15a18_PORT_B_address_reg, L1_ram_block15a18_PORT_A_write_enable_reg, L1_ram_block15a18_PORT_B_read_enable_reg, , , L1_ram_block15a18_clock_0, L1_ram_block15a18_clock_1, L1_ram_block15a18_clock_enable_0, L1_ram_block15a18_clock_enable_1, , );
L1_ram_block15a18 = L1_ram_block15a18_PORT_B_data_out[0];


--L1_ram_block15a17 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a17
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a17_PORT_A_data_in = data_in;
L1_ram_block15a17_PORT_A_data_in_reg = DFFE(L1_ram_block15a17_PORT_A_data_in, L1_ram_block15a17_clock_0, , , L1_ram_block15a17_clock_enable_0);
L1_ram_block15a17_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a17_PORT_A_address_reg = DFFE(L1_ram_block15a17_PORT_A_address, L1_ram_block15a17_clock_0, , , L1_ram_block15a17_clock_enable_0);
L1_ram_block15a17_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a17_PORT_B_address_reg = DFFE(L1_ram_block15a17_PORT_B_address, L1_ram_block15a17_clock_1, , , L1_ram_block15a17_clock_enable_1);
L1_ram_block15a17_PORT_A_write_enable = VCC;
L1_ram_block15a17_PORT_A_write_enable_reg = DFFE(L1_ram_block15a17_PORT_A_write_enable, L1_ram_block15a17_clock_0, , , L1_ram_block15a17_clock_enable_0);
L1_ram_block15a17_PORT_B_read_enable = VCC;
L1_ram_block15a17_PORT_B_read_enable_reg = DFFE(L1_ram_block15a17_PORT_B_read_enable, L1_ram_block15a17_clock_1, , , L1_ram_block15a17_clock_enable_1);
L1_ram_block15a17_clock_0 = clk_in;
L1_ram_block15a17_clock_1 = B1_clkdiv;
L1_ram_block15a17_clock_enable_0 = M1_w_anode585w[3];
L1_ram_block15a17_clock_enable_1 = F1_w2w;
L1_ram_block15a17_PORT_B_data_out = MEMORY(L1_ram_block15a17_PORT_A_data_in_reg, , L1_ram_block15a17_PORT_A_address_reg, L1_ram_block15a17_PORT_B_address_reg, L1_ram_block15a17_PORT_A_write_enable_reg, L1_ram_block15a17_PORT_B_read_enable_reg, , , L1_ram_block15a17_clock_0, L1_ram_block15a17_clock_1, L1_ram_block15a17_clock_enable_0, L1_ram_block15a17_clock_enable_1, , );
L1_ram_block15a17 = L1_ram_block15a17_PORT_B_data_out[0];


--L1_ram_block15a16 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a16
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a16_PORT_A_data_in = data_in;