buffer422.map.eqn

一个同步422接口控制器的verilog源程序。

L1_ram_block15a20_PORT_A_write_enable_reg = DFFE(L1_ram_block15a20_PORT_A_write_enable, L1_ram_block15a20_clock_0, , , L1_ram_block15a20_clock_enable_0);
L1_ram_block15a20_PORT_B_read_enable = VCC;
L1_ram_block15a20_PORT_B_read_enable_reg = DFFE(L1_ram_block15a20_PORT_B_read_enable, L1_ram_block15a20_clock_1, , , L1_ram_block15a20_clock_enable_1);
L1_ram_block15a20_clock_0 = clk_in;
L1_ram_block15a20_clock_1 = B1_clkdiv;
L1_ram_block15a20_clock_enable_0 = M1_w_anode615w[3];
L1_ram_block15a20_clock_enable_1 = F1_w2w;
L1_ram_block15a20_PORT_B_data_out = MEMORY(L1_ram_block15a20_PORT_A_data_in_reg, , L1_ram_block15a20_PORT_A_address_reg, L1_ram_block15a20_PORT_B_address_reg, L1_ram_block15a20_PORT_A_write_enable_reg, L1_ram_block15a20_PORT_B_read_enable_reg, , , L1_ram_block15a20_clock_0, L1_ram_block15a20_clock_1, L1_ram_block15a20_clock_enable_0, L1_ram_block15a20_clock_enable_1, , );
L1_ram_block15a20 = L1_ram_block15a20_PORT_B_data_out[0];


--N1L11 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|mux_6o7:mux17|w_result1004w~44
--operation mode is normal

N1L11 = L1_address_reg_b[1] & (L1_address_reg_b[0]) # !L1_address_reg_b[1] & (L1_address_reg_b[0] & L1_ram_block15a21 # !L1_address_reg_b[0] & (L1_ram_block15a20));


--L1_ram_block15a23 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a23
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a23_PORT_A_data_in = data_in;
L1_ram_block15a23_PORT_A_data_in_reg = DFFE(L1_ram_block15a23_PORT_A_data_in, L1_ram_block15a23_clock_0, , , L1_ram_block15a23_clock_enable_0);
L1_ram_block15a23_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a23_PORT_A_address_reg = DFFE(L1_ram_block15a23_PORT_A_address, L1_ram_block15a23_clock_0, , , L1_ram_block15a23_clock_enable_0);
L1_ram_block15a23_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a23_PORT_B_address_reg = DFFE(L1_ram_block15a23_PORT_B_address, L1_ram_block15a23_clock_1, , , L1_ram_block15a23_clock_enable_1);
L1_ram_block15a23_PORT_A_write_enable = VCC;
L1_ram_block15a23_PORT_A_write_enable_reg = DFFE(L1_ram_block15a23_PORT_A_write_enable, L1_ram_block15a23_clock_0, , , L1_ram_block15a23_clock_enable_0);
L1_ram_block15a23_PORT_B_read_enable = VCC;
L1_ram_block15a23_PORT_B_read_enable_reg = DFFE(L1_ram_block15a23_PORT_B_read_enable, L1_ram_block15a23_clock_1, , , L1_ram_block15a23_clock_enable_1);
L1_ram_block15a23_clock_0 = clk_in;
L1_ram_block15a23_clock_1 = B1_clkdiv;
L1_ram_block15a23_clock_enable_0 = M1_w_anode645w[3];
L1_ram_block15a23_clock_enable_1 = F1_w2w;
L1_ram_block15a23_PORT_B_data_out = MEMORY(L1_ram_block15a23_PORT_A_data_in_reg, , L1_ram_block15a23_PORT_A_address_reg, L1_ram_block15a23_PORT_B_address_reg, L1_ram_block15a23_PORT_A_write_enable_reg, L1_ram_block15a23_PORT_B_read_enable_reg, , , L1_ram_block15a23_clock_0, L1_ram_block15a23_clock_1, L1_ram_block15a23_clock_enable_0, L1_ram_block15a23_clock_enable_1, , );
L1_ram_block15a23 = L1_ram_block15a23_PORT_B_data_out[0];


--N1L21 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|mux_6o7:mux17|w_result1004w~45
--operation mode is normal

N1L21 = L1_address_reg_b[1] & (N1L11 & (L1_ram_block15a23) # !N1L11 & L1_ram_block15a22) # !L1_address_reg_b[1] & (N1L11);


--L1_ram_block15a5 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a5
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a5_PORT_A_data_in = data_in;
L1_ram_block15a5_PORT_A_data_in_reg = DFFE(L1_ram_block15a5_PORT_A_data_in, L1_ram_block15a5_clock_0, , , L1_ram_block15a5_clock_enable_0);
L1_ram_block15a5_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a5_PORT_A_address_reg = DFFE(L1_ram_block15a5_PORT_A_address, L1_ram_block15a5_clock_0, , , L1_ram_block15a5_clock_enable_0);
L1_ram_block15a5_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a5_PORT_B_address_reg = DFFE(L1_ram_block15a5_PORT_B_address, L1_ram_block15a5_clock_1, , , L1_ram_block15a5_clock_enable_1);
L1_ram_block15a5_PORT_A_write_enable = VCC;
L1_ram_block15a5_PORT_A_write_enable_reg = DFFE(L1_ram_block15a5_PORT_A_write_enable, L1_ram_block15a5_clock_0, , , L1_ram_block15a5_clock_enable_0);
L1_ram_block15a5_PORT_B_read_enable = VCC;
L1_ram_block15a5_PORT_B_read_enable_reg = DFFE(L1_ram_block15a5_PORT_B_read_enable, L1_ram_block15a5_clock_1, , , L1_ram_block15a5_clock_enable_1);
L1_ram_block15a5_clock_0 = clk_in;
L1_ram_block15a5_clock_1 = B1_clkdiv;
L1_ram_block15a5_clock_enable_0 = M1_w_anode442w[3];
L1_ram_block15a5_clock_enable_1 = F1_w2w;
L1_ram_block15a5_PORT_B_data_out = MEMORY(L1_ram_block15a5_PORT_A_data_in_reg, , L1_ram_block15a5_PORT_A_address_reg, L1_ram_block15a5_PORT_B_address_reg, L1_ram_block15a5_PORT_A_write_enable_reg, L1_ram_block15a5_PORT_B_read_enable_reg, , , L1_ram_block15a5_clock_0, L1_ram_block15a5_clock_1, L1_ram_block15a5_clock_enable_0, L1_ram_block15a5_clock_enable_1, , );
L1_ram_block15a5 = L1_ram_block15a5_PORT_B_data_out[0];


--L1_ram_block15a6 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a6
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a6_PORT_A_data_in = data_in;
L1_ram_block15a6_PORT_A_data_in_reg = DFFE(L1_ram_block15a6_PORT_A_data_in, L1_ram_block15a6_clock_0, , , L1_ram_block15a6_clock_enable_0);
L1_ram_block15a6_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a6_PORT_A_address_reg = DFFE(L1_ram_block15a6_PORT_A_address, L1_ram_block15a6_clock_0, , , L1_ram_block15a6_clock_enable_0);
L1_ram_block15a6_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a6_PORT_B_address_reg = DFFE(L1_ram_block15a6_PORT_B_address, L1_ram_block15a6_clock_1, , , L1_ram_block15a6_clock_enable_1);
L1_ram_block15a6_PORT_A_write_enable = VCC;
L1_ram_block15a6_PORT_A_write_enable_reg = DFFE(L1_ram_block15a6_PORT_A_write_enable, L1_ram_block15a6_clock_0, , , L1_ram_block15a6_clock_enable_0);
L1_ram_block15a6_PORT_B_read_enable = VCC;
L1_ram_block15a6_PORT_B_read_enable_reg = DFFE(L1_ram_block15a6_PORT_B_read_enable, L1_ram_block15a6_clock_1, , , L1_ram_block15a6_clock_enable_1);
L1_ram_block15a6_clock_0 = clk_in;
L1_ram_block15a6_clock_1 = B1_clkdiv;
L1_ram_block15a6_clock_enable_0 = M1_w_anode452w[3];
L1_ram_block15a6_clock_enable_1 = F1_w2w;
L1_ram_block15a6_PORT_B_data_out = MEMORY(L1_ram_block15a6_PORT_A_data_in_reg, , L1_ram_block15a6_PORT_A_address_reg, L1_ram_block15a6_PORT_B_address_reg, L1_ram_block15a6_PORT_A_write_enable_reg, L1_ram_block15a6_PORT_B_read_enable_reg, , , L1_ram_block15a6_clock_0, L1_ram_block15a6_clock_1, L1_ram_block15a6_clock_enable_0, L1_ram_block15a6_clock_enable_1, , );
L1_ram_block15a6 = L1_ram_block15a6_PORT_B_data_out[0];


--L1_ram_block15a4 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a4
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a4_PORT_A_data_in = data_in;
L1_ram_block15a4_PORT_A_data_in_reg = DFFE(L1_ram_block15a4_PORT_A_data_in, L1_ram_block15a4_clock_0, , , L1_ram_block15a4_clock_enable_0);
L1_ram_block15a4_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a4_PORT_A_address_reg = DFFE(L1_ram_block15a4_PORT_A_address, L1_ram_block15a4_clock_0, , , L1_ram_block15a4_clock_enable_0);
L1_ram_block15a4_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a4_PORT_B_address_reg = DFFE(L1_ram_block15a4_PORT_B_address, L1_ram_block15a4_clock_1, , , L1_ram_block15a4_clock_enable_1);
L1_ram_block15a4_PORT_A_write_enable = VCC;
L1_ram_block15a4_PORT_A_write_enable_reg = DFFE(L1_ram_block15a4_PORT_A_write_enable, L1_ram_block15a4_clock_0, , , L1_ram_block15a4_clock_enable_0);
L1_ram_block15a4_PORT_B_read_enable = VCC;
L1_ram_block15a4_PORT_B_read_enable_reg = DFFE(L1_ram_block15a4_PORT_B_read_enable, L1_ram_block15a4_clock_1, , , L1_ram_block15a4_clock_enable_1);
L1_ram_block15a4_clock_0 = clk_in;
L1_ram_block15a4_clock_1 = B1_clkdiv;
L1_ram_block15a4_clock_enable_0 = M1_w_anode432w[3];
L1_ram_block15a4_clock_enable_1 = F1_w2w;
L1_ram_block15a4_PORT_B_data_out = MEMORY(L1_ram_block15a4_PORT_A_data_in_reg, , L1_ram_block15a4_PORT_A_address_reg, L1_ram_block15a4_PORT_B_address_reg, L1_ram_block15a4_PORT_A_write_enable_reg, L1_ram_block15a4_PORT_B_read_enable_reg, , , L1_ram_block15a4_clock_0, L1_ram_block15a4_clock_1, L1_ram_block15a4_clock_enable_0, L1_ram_block15a4_clock_enable_1, , );
L1_ram_block15a4 = L1_ram_block15a4_PORT_B_data_out[0];


--N1L1 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|mux_6o7:mux17|w_result902w~44
--operation mode is normal

N1L1 = L1_address_reg_b[0] & (L1_address_reg_b[1]) # !L1_address_reg_b[0] & (L1_address_reg_b[1] & L1_ram_block15a6 # !L1_address_reg_b[1] & (L1_ram_block15a4));


--L1_ram_block15a7 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a7
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a7_PORT_A_data_in = data_in;
L1_ram_block15a7_PORT_A_data_in_reg = DFFE(L1_ram_block15a7_PORT_A_data_in, L1_ram_block15a7_clock_0, , , L1_ram_block15a7_clock_enable_0);
L1_ram_block15a7_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a7_PORT_A_address_reg = DFFE(L1_ram_block15a7_PORT_A_address, L1_ram_block15a7_clock_0, , , L1_ram_block15a7_clock_enable_0);
L1_ram_block15a7_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a7_PORT_B_address_reg = DFFE(L1_ram_block15a7_PORT_B_address, L1_ram_block15a7_clock_1, , , L1_ram_block15a7_clock_enable_1);
L1_ram_block15a7_PORT_A_write_enable = VCC;
L1_ram_block15a7_PORT_A_write_enable_reg = DFFE(L1_ram_block15a7_PORT_A_write_enable, L1_ram_block15a7_clock_0, , , L1_ram_block15a7_clock_enable_0);
L1_ram_block15a7_PORT_B_read_enable = VCC;
L1_ram_block15a7_PORT_B_read_enable_reg = DFFE(L1_ram_block15a7_PORT_B_read_enable, L1_ram_block15a7_clock_1, , , L1_ram_block15a7_clock_enable_1);
L1_ram_block15a7_clock_0 = clk_in;
L1_ram_block15a7_clock_1 = B1_clkdiv;
L1_ram_block15a7_clock_enable_0 = M1_w_anode462w[3];
L1_ram_block15a7_clock_enable_1 = F1_w2w;
L1_ram_block15a7_PORT_B_data_out = MEMORY(L1_ram_block15a7_PORT_A_data_in_reg, , L1_ram_block15a7_PORT_A_address_reg, L1_ram_block15a7_PORT_B_address_reg, L1_ram_block15a7_PORT_A_write_enable_reg, L1_ram_block15a7_PORT_B_read_enable_reg, , , L1_ram_block15a7_clock_0, L1_ram_block15a7_clock_1, L1_ram_block15a7_clock_enable_0, L1_ram_block15a7_clock_enable_1, , );
L1_ram_block15a7 = L1_ram_block15a7_PORT_B_data_out[0];


--N1L2 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|mux_6o7:mux17|w_result902w~45
--operation mode is normal

N1L2 = L1_address_reg_b[0] & (N1L1 & (L1_ram_block15a7) # !N1L1 & L1_ram_block15a5) # !L1_address_reg_b[0] & (N1L1);


--L1_address_reg_b[4] is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|address_reg_b[4]
--operation mode is normal

L1_address_reg_b[4]_lut_out = F1_dffe5a[16];
L1_address_reg_b[4] = DFFEAS(L1_address_reg_b[4]_lut_out, B1_clkdiv, VCC, , F1_w2w, , , , );


--B1L52 is buff_control:inst|dout~440
--operation mode is normal

B1L52 = L1_address_reg_b[4] & N1L21 # !L1_address_reg_b[4] & (N1L2);


--L1_address_reg_b[3] is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|address_reg_b[3]
--operation mode is normal

L1_address_reg_b[3]_lut_out = F1_dffe5a[15];
L1_address_reg_b[3] = DFFEAS(L1_address_reg_b[3]_lut_out, B1_clkdiv, VCC, , F1_w2w, , , , );