buffer422.map.eqn

一个同步422接口控制器的verilog源程序。

H1L42_carry_eqn = H1L72;
H1L42 = F1_dffe8a[4] $ F1_dffe5a[4] $ H1L42_carry_eqn;

--H1L52 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_h18:add_sub3|add_sub_cella[0]~522
--operation mode is arithmetic

H1L52 = CARRY(F1_dffe8a[4] & (!H1L72 # !F1_dffe5a[4]) # !F1_dffe8a[4] & !F1_dffe5a[4] & !H1L72);


--H1L62 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_h18:add_sub3|add_sub_cella[0]~525
--operation mode is arithmetic

H1L62_carry_eqn = H1L92;
H1L62 = F1_dffe8a[3] $ F1_dffe5a[3] $ !H1L62_carry_eqn;

--H1L72 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_h18:add_sub3|add_sub_cella[0]~527
--operation mode is arithmetic

H1L72 = CARRY(F1_dffe8a[3] & F1_dffe5a[3] & !H1L92 # !F1_dffe8a[3] & (F1_dffe5a[3] # !H1L92));


--H1L82 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_h18:add_sub3|add_sub_cella[0]~530
--operation mode is arithmetic

H1L82_carry_eqn = H1L13;
H1L82 = F1_dffe8a[2] $ F1_dffe5a[2] $ H1L82_carry_eqn;

--H1L92 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_h18:add_sub3|add_sub_cella[0]~532
--operation mode is arithmetic

H1L92 = CARRY(F1_dffe8a[2] & (!H1L13 # !F1_dffe5a[2]) # !F1_dffe8a[2] & !F1_dffe5a[2] & !H1L13);


--H1L03 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_h18:add_sub3|add_sub_cella[0]~535
--operation mode is arithmetic

H1L03_carry_eqn = H1L33;
H1L03 = F1_dffe8a[1] $ F1_dffe5a[1] $ !H1L03_carry_eqn;

--H1L13 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_h18:add_sub3|add_sub_cella[0]~537
--operation mode is arithmetic

H1L13 = CARRY(F1_dffe8a[1] & F1_dffe5a[1] & !H1L33 # !F1_dffe8a[1] & (F1_dffe5a[1] # !H1L33));


--H1L23 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_h18:add_sub3|add_sub_cella[0]~540
--operation mode is arithmetic

H1L23 = F1_dffe8a[0] $ F1_dffe5a[0];

--H1L33 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|add_sub_h18:add_sub3|add_sub_cella[0]~542
--operation mode is arithmetic

H1L33 = CARRY(F1_dffe8a[0] # !F1_dffe5a[0]);


--B1_clcnt[1] is buff_control:inst|clcnt[1]
--operation mode is normal

B1_clcnt[1]_lut_out = !B1_clcnt[2] & (B1_clcnt[1] $ B1_clcnt[0]);
B1_clcnt[1] = DFFEAS(B1_clcnt[1]_lut_out, clk, rst, , , , , , );


--B1_clcnt[2] is buff_control:inst|clcnt[2]
--operation mode is normal

B1_clcnt[2]_lut_out = B1_clcnt[2] & (!B1_clcnt[1] & !B1_clcnt[0]) # !B1_clcnt[2] & (B1_clcnt[1] & B1_clcnt[0]);
B1_clcnt[2] = DFFEAS(B1_clcnt[2]_lut_out, clk, rst, , , , , , );


--B1_clcnt[0] is buff_control:inst|clcnt[0]
--operation mode is normal

B1_clcnt[0]_lut_out = !B1_clcnt[0] & (!B1_clcnt[1] # !B1_clcnt[2]);
B1_clcnt[0] = DFFEAS(B1_clcnt[0]_lut_out, clk, rst, , , , , , );


--B1L201 is buff_control:inst|reduce_nor~0
--operation mode is normal

B1L201 = !B1_clcnt[1] & (B1_clcnt[2] & B1_clcnt[0]);


--L1_address_reg_b[2] is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|address_reg_b[2]
--operation mode is normal

L1_address_reg_b[2]_lut_out = F1_dffe5a[14];
L1_address_reg_b[2] = DFFEAS(L1_address_reg_b[2]_lut_out, B1_clkdiv, VCC, , F1_w2w, , , , );


--B1_active is buff_control:inst|active
--operation mode is normal

B1_active_lut_out = H1L1 # B1_active & B1L6;
B1_active = DFFEAS(B1_active_lut_out, B1_clkdiv, rst, , , , , , );


--L1_ram_block15a22 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a22
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a22_PORT_A_data_in = data_in;
L1_ram_block15a22_PORT_A_data_in_reg = DFFE(L1_ram_block15a22_PORT_A_data_in, L1_ram_block15a22_clock_0, , , L1_ram_block15a22_clock_enable_0);
L1_ram_block15a22_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a22_PORT_A_address_reg = DFFE(L1_ram_block15a22_PORT_A_address, L1_ram_block15a22_clock_0, , , L1_ram_block15a22_clock_enable_0);
L1_ram_block15a22_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a22_PORT_B_address_reg = DFFE(L1_ram_block15a22_PORT_B_address, L1_ram_block15a22_clock_1, , , L1_ram_block15a22_clock_enable_1);
L1_ram_block15a22_PORT_A_write_enable = VCC;
L1_ram_block15a22_PORT_A_write_enable_reg = DFFE(L1_ram_block15a22_PORT_A_write_enable, L1_ram_block15a22_clock_0, , , L1_ram_block15a22_clock_enable_0);
L1_ram_block15a22_PORT_B_read_enable = VCC;
L1_ram_block15a22_PORT_B_read_enable_reg = DFFE(L1_ram_block15a22_PORT_B_read_enable, L1_ram_block15a22_clock_1, , , L1_ram_block15a22_clock_enable_1);
L1_ram_block15a22_clock_0 = clk_in;
L1_ram_block15a22_clock_1 = B1_clkdiv;
L1_ram_block15a22_clock_enable_0 = M1_w_anode635w[3];
L1_ram_block15a22_clock_enable_1 = F1_w2w;
L1_ram_block15a22_PORT_B_data_out = MEMORY(L1_ram_block15a22_PORT_A_data_in_reg, , L1_ram_block15a22_PORT_A_address_reg, L1_ram_block15a22_PORT_B_address_reg, L1_ram_block15a22_PORT_A_write_enable_reg, L1_ram_block15a22_PORT_B_read_enable_reg, , , L1_ram_block15a22_clock_0, L1_ram_block15a22_clock_1, L1_ram_block15a22_clock_enable_0, L1_ram_block15a22_clock_enable_1, , );
L1_ram_block15a22 = L1_ram_block15a22_PORT_B_data_out[0];


--L1_address_reg_b[1] is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|address_reg_b[1]
--operation mode is normal

L1_address_reg_b[1]_lut_out = F1_dffe5a[13];
L1_address_reg_b[1] = DFFEAS(L1_address_reg_b[1]_lut_out, B1_clkdiv, VCC, , F1_w2w, , , , );


--L1_ram_block15a21 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a21
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a21_PORT_A_data_in = data_in;
L1_ram_block15a21_PORT_A_data_in_reg = DFFE(L1_ram_block15a21_PORT_A_data_in, L1_ram_block15a21_clock_0, , , L1_ram_block15a21_clock_enable_0);
L1_ram_block15a21_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a21_PORT_A_address_reg = DFFE(L1_ram_block15a21_PORT_A_address, L1_ram_block15a21_clock_0, , , L1_ram_block15a21_clock_enable_0);
L1_ram_block15a21_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a21_PORT_B_address_reg = DFFE(L1_ram_block15a21_PORT_B_address, L1_ram_block15a21_clock_1, , , L1_ram_block15a21_clock_enable_1);
L1_ram_block15a21_PORT_A_write_enable = VCC;
L1_ram_block15a21_PORT_A_write_enable_reg = DFFE(L1_ram_block15a21_PORT_A_write_enable, L1_ram_block15a21_clock_0, , , L1_ram_block15a21_clock_enable_0);
L1_ram_block15a21_PORT_B_read_enable = VCC;
L1_ram_block15a21_PORT_B_read_enable_reg = DFFE(L1_ram_block15a21_PORT_B_read_enable, L1_ram_block15a21_clock_1, , , L1_ram_block15a21_clock_enable_1);
L1_ram_block15a21_clock_0 = clk_in;
L1_ram_block15a21_clock_1 = B1_clkdiv;
L1_ram_block15a21_clock_enable_0 = M1_w_anode625w[3];
L1_ram_block15a21_clock_enable_1 = F1_w2w;
L1_ram_block15a21_PORT_B_data_out = MEMORY(L1_ram_block15a21_PORT_A_data_in_reg, , L1_ram_block15a21_PORT_A_address_reg, L1_ram_block15a21_PORT_B_address_reg, L1_ram_block15a21_PORT_A_write_enable_reg, L1_ram_block15a21_PORT_B_read_enable_reg, , , L1_ram_block15a21_clock_0, L1_ram_block15a21_clock_1, L1_ram_block15a21_clock_enable_0, L1_ram_block15a21_clock_enable_1, , );
L1_ram_block15a21 = L1_ram_block15a21_PORT_B_data_out[0];


--L1_address_reg_b[0] is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|address_reg_b[0]
--operation mode is normal

L1_address_reg_b[0]_lut_out = F1_dffe5a[12];
L1_address_reg_b[0] = DFFEAS(L1_address_reg_b[0]_lut_out, B1_clkdiv, VCC, , F1_w2w, , , , );


--L1_ram_block15a20 is lpm_fifo0:inst1|dcfifo:dcfifo_component|dcfifo_gfu:auto_generated|alt_sync_fifo_fjm:sync_fifo|dpram_hpm:dpram4|altsyncram_sia1:altsyncram14|ram_block15a20
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 131072, Port A Logical Width: 1, Port B Logical Depth: 131072, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_ram_block15a20_PORT_A_data_in = data_in;
L1_ram_block15a20_PORT_A_data_in_reg = DFFE(L1_ram_block15a20_PORT_A_data_in, L1_ram_block15a20_clock_0, , , L1_ram_block15a20_clock_enable_0);
L1_ram_block15a20_PORT_A_address = BUS(J1_safe_q[0], J1_safe_q[1], J1_safe_q[2], J1_safe_q[3], J1_safe_q[4], J1_safe_q[5], J1_safe_q[6], J1_safe_q[7], J1_safe_q[8], J1_safe_q[9], J1_safe_q[10], J1_safe_q[11]);
L1_ram_block15a20_PORT_A_address_reg = DFFE(L1_ram_block15a20_PORT_A_address, L1_ram_block15a20_clock_0, , , L1_ram_block15a20_clock_enable_0);
L1_ram_block15a20_PORT_B_address = BUS(F1_dffe5a[0], F1_dffe5a[1], F1_dffe5a[2], F1_dffe5a[3], F1_dffe5a[4], F1_dffe5a[5], F1_dffe5a[6], F1_dffe5a[7], F1_dffe5a[8], F1_dffe5a[9], F1_dffe5a[10], F1_dffe5a[11]);
L1_ram_block15a20_PORT_B_address_reg = DFFE(L1_ram_block15a20_PORT_B_address, L1_ram_block15a20_clock_1, , , L1_ram_block15a20_clock_enable_1);
L1_ram_block15a20_PORT_A_write_enable = VCC;