📄 stm32f10x_i2c.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 914] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\rvmdk\stm32f10x_i2c.o --depend=.\rvmdk\stm32f10x_i2c.d --device=DARMSTM -O1 -Otime -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -I..\..\..\..\..\uC-Probe\Target\Plugins\uCOS-II -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\Source -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Ports\ST\STM32 -I..\..\..\..\..\uC-Probe\Target\Communication\Generic\RS-232\Source -ID:\Keil\ARM\INC\ST\STM32F10x ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_i2c.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
I2C_DeInit PROC
;;;114 void I2C_DeInit(I2C_TypeDef* I2Cx)
;;;115 {
000000 b510 PUSH {r4,lr}
;;;116 switch (*(u32*)&I2Cx)
000002 f1a0f1a0 SUB r0,r0,#0x40000000
000006 f5b0f5b0 SUBS r0,r0,#0x5400
00000a d00d BEQ |L1.40|
00000c f5b0f5b0 CMP r0,#0x400
000010 d115 BNE |L1.62|
000012 2101 MOVS r1,#1
000014 0588 LSLS r0,r1,#22
000016 f7fff7ff BL RCC_APB1PeriphResetCmd
00001a e8bde8bd POP {r4,lr}
00001e 2100 MOVS r1,#0
000020 f44ff44f MOV r0,#0x400000
000024 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.40|
;;;117 {
;;;118 case I2C1_BASE:
;;;119 /* Enable I2C1 reset state */
;;;120 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
000028 2101 MOVS r1,#1
00002a 0548 LSLS r0,r1,#21
00002c f7fff7ff BL RCC_APB1PeriphResetCmd
;;;121 /* Release I2C1 from reset state */
;;;122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
000030 e8bde8bd POP {r4,lr}
000034 2100 MOVS r1,#0
000036 f44ff44f MOV r0,#0x200000
00003a f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.62|
;;;123 break;
;;;124
;;;125 case I2C2_BASE:
;;;126 /* Enable I2C2 reset state */
;;;127 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
;;;128 /* Release I2C2 from reset state */
;;;129 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
;;;130 break;
;;;131
;;;132 default:
;;;133 break;
;;;134 }
;;;135 }
00003e bd10 POP {r4,pc}
;;;136
ENDP
I2C_Cmd PROC
;;;293
;;;294 if (NewState != DISABLE)
000040 b121 CBZ r1,|L1.76|
;;;295 {
;;;296 /* Enable the selected I2C peripheral */
;;;297 I2Cx->CR1 |= CR1_PE_Set;
000042 8801 LDRH r1,[r0,#0]
000044 f041f041 ORR r1,r1,#1
000048 8001 STRH r1,[r0,#0]
;;;298 }
;;;299 else
;;;300 {
;;;301 /* Disable the selected I2C peripheral */
;;;302 I2Cx->CR1 &= CR1_PE_Reset;
;;;303 }
;;;304 }
00004a 4770 BX lr
|L1.76|
00004c 8801 LDRH r1,[r0,#0]
00004e f021f021 BIC r1,r1,#1
000052 8001 STRH r1,[r0,#0]
000054 4770 BX lr
;;;305
ENDP
I2C_Init PROC
;;;148 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
;;;149 {
000056 b570 PUSH {r4-r6,lr}
000058 b086 SUB sp,sp,#0x18
00005a 4604 MOV r4,r0
00005c 460d MOV r5,r1
;;;150 u16 tmpreg = 0, freqrange = 0;
;;;151 u16 result = 0x04;
;;;152 u32 pclk1clock = 12000000;
;;;153 RCC_ClocksTypeDef RCC_Clocks;
;;;154
;;;155 /* Check the parameters */
;;;156 assert(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
;;;157 assert(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
;;;158 assert(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
;;;159 assert(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
;;;160 assert(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
;;;161 assert(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
;;;162
;;;163 /*---------------------------- I2Cx CR2 Configuration ------------------------*/
;;;164 /* Get the I2Cx CR2 value */
;;;165 tmpreg = I2Cx->CR2;
00005e 88a0 LDRH r0,[r4,#4]
;;;166 /* Clear frequency FREQ[5:0] bits */
;;;167 tmpreg &= CR2_FREQ_Reset;
000060 f020f020 BIC r6,r0,#0x3f
;;;168 /* Get PCLK1Clock frequency value */
;;;169 RCC_GetClocksFreq(&RCC_Clocks);
000064 a801 ADD r0,sp,#4
000066 f7fff7ff BL RCC_GetClocksFreq
;;;170 pclk1clock = RCC_Clocks.PCLK1_Frequency;
00006a 9a03 LDR r2,[sp,#0xc]
;;;171 /* Set frequency bits depending on PCLK1Clock value */
;;;172 freqrange = (u16)(pclk1clock / 1000000);
00006c 48c4 LDR r0,|L1.896|
00006e fbb2fbb2 UDIV r0,r2,r0
000072 b283 UXTH r3,r0
;;;173 tmpreg |= freqrange;
000074 ea46ea46 ORR r0,r6,r3
;;;174 /* Write to I2Cx CR2 */
;;;175 I2Cx->CR2 = tmpreg;
000078 80a0 STRH r0,[r4,#4]
;;;176
;;;177 /*---------------------------- I2Cx CCR Configuration ------------------------*/
;;;178 /* Disable I2Cx to configure TRISE */
;;;179 I2C_Cmd(I2Cx, DISABLE);
00007a 2100 MOVS r1,#0
00007c 4620 MOV r0,r4
00007e f7fff7ff BL I2C_Cmd
;;;180
;;;181 /* Reset tmpreg value */
;;;182 /* Clear F/S, DUTY and CCR[11:0] bits */
;;;183 tmpreg = 0;
;;;184
;;;185 /* Configure speed in standard mode */
;;;186 if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
000082 49c0 LDR r1,|L1.900|
000084 68e8 LDR r0,[r5,#0xc]
000086 4288 CMP r0,r1
000088 d809 BHI |L1.158|
;;;187 {
;;;188 /* Standard mode speed calculate */
;;;189 result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed << 1));
00008a 0040 LSLS r0,r0,#1
00008c fbb2fbb2 UDIV r0,r2,r0
000090 b280 UXTH r0,r0
;;;190 /* Test if CCR value is under 0x4*/
;;;191 if (result < 0x04)
000092 2804 CMP r0,#4
000094 d200 BCS |L1.152|
;;;192 {
;;;193 /* Set minimum allowed value */
;;;194 result = 0x04;
000096 2004 MOVS r0,#4
|L1.152|
;;;195 }
;;;196 /* Set speed value for standard mode */
;;;197 tmpreg |= result;
;;;198 /* Set Maximum Rise Time: ((1000/(1000000000/pclk1clock))+1 */
;;;199 I2Cx->TRISE = freqrange + 1;
000098 1c59 ADDS r1,r3,#1
00009a 8421 STRH r1,[r4,#0x20]
00009c e022 B |L1.228|
|L1.158|
;;;200 }
;;;201 /* Configure speed in fast mode */
;;;202 else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
;;;203 {
;;;204 if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
00009e 8869 LDRH r1,[r5,#2]
0000a0 f5a1f5a1 SUB r12,r1,#0xbf00
0000a4 f1bcf1bc SUBS r12,r12,#0xff
0000a8 d105 BNE |L1.182|
;;;205 {
;;;206 /* Fast mode speed calculate: Tlow/Thigh = 2 */
;;;207 result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 3));
0000aa eb00eb00 ADD r0,r0,r0,LSL #1
0000ae fbb2fbb2 UDIV r0,r2,r0
0000b2 b280 UXTH r0,r0
0000b4 e006 B |L1.196|
|L1.182|
;;;208 }
;;;209 else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
;;;210 {
;;;211 /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
;;;212 result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 25));
0000b6 2119 MOVS r1,#0x19
0000b8 4348 MULS r0,r1,r0
0000ba fbb2fbb2 UDIV r0,r2,r0
0000be b280 UXTH r0,r0
;;;213 /* Set DUTY bit */
;;;214 result |= I2C_DutyCycle_16_9;
0000c0 f440f440 ORR r0,r0,#0x4000
|L1.196|
;;;215 }
;;;216 /* Test if CCR value is under 0x1*/
;;;217 if ((result & CCR_CCR_Set) == 0)
0000c4 0501 LSLS r1,r0,#20
0000c6 0d09 LSRS r1,r1,#20
0000c8 d101 BNE |L1.206|
;;;218 {
;;;219 /* Set minimum allowed value */
;;;220 result |= (u16)0x0001;
0000ca f040f040 ORR r0,r0,#1
|L1.206|
;;;221 }
;;;222 /* Set speed value and set F/S bit for fast mode */
;;;223 tmpreg |= result | CCR_FS_Set;
0000ce f440f440 ORR r0,r0,#0x8000
;;;224 /* Set Maximum Rise Time: ((300/(1000000000/pclk1clock))+1 */
;;;225 I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1);
0000d2 f44ff44f MOV r1,#0x12c
0000d6 4359 MULS r1,r3,r1
0000d8 f44ff44f MOV r2,#0x3e8
0000dc fbb1fbb1 UDIV r1,r1,r2
0000e0 1c49 ADDS r1,r1,#1
0000e2 8421 STRH r1,[r4,#0x20]
|L1.228|
;;;226 }
;;;227 /* Write to I2Cx CCR */
;;;228 I2Cx->CCR = tmpreg;
0000e4 83a0 STRH r0,[r4,#0x1c]
;;;229
;;;230 /* Enable I2Cx */
;;;231 I2C_Cmd(I2Cx, ENABLE);
0000e6 2101 MOVS r1,#1
0000e8 4620 MOV r0,r4
0000ea f7fff7ff BL I2C_Cmd
;;;232
;;;233 /*---------------------------- I2Cx CR1 Configuration ------------------------*/
;;;234 /* Get the I2Cx CR1 value */
;;;235 tmpreg = I2Cx->CR1;
0000ee 8820 LDRH r0,[r4,#0]
;;;236 /* Clear ACK, SMBTYPE and SMBUS bits */
;;;237 tmpreg &= CR1_CLEAR_Mask;
0000f0 f020f020 BIC r0,r0,#0xa
0000f4 f420f420 BIC r0,r0,#0x400
;;;238 /* Configure I2Cx: mode and acknowledgement */
;;;239 /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
;;;240 /* Set ACK bit according to I2C_Ack value */
;;;241 tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
0000f8 8829 LDRH r1,[r5,#0]
0000fa 88ea LDRH r2,[r5,#6]
0000fc 4311 ORRS r1,r1,r2
0000fe 4308 ORRS r0,r0,r1
;;;242 /* Write to I2Cx CR1 */
;;;243 I2Cx->CR1 = tmpreg;
000100 8020 STRH r0,[r4,#0]
;;;244
;;;245 /*---------------------------- I2Cx OAR1 Configuration -----------------------*/
;;;246 /* Set I2Cx Own Address1 and acknowledged address */
;;;247 I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
000102 8928 LDRH r0,[r5,#8]
000104 88a9 LDRH r1,[r5,#4]
000106 4308 ORRS r0,r0,r1
000108 8120 STRH r0,[r4,#8]
;;;248 }
00010a b006 ADD sp,sp,#0x18
00010c bd70 POP {r4-r6,pc}
;;;249
ENDP
I2C_StructInit PROC
;;;261 /* Initialize the I2C_Mode member */
;;;262 I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
00010e 2100 MOVS r1,#0
000110 8001 STRH r1,[r0,#0]
;;;263
;;;264 /* Initialize the I2C_DutyCycle member */
;;;265 I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
000112 f64bf64b MOV r2,#0xbfff
000116 8042 STRH r2,[r0,#2]
;;;266
;;;267 /* Initialize the I2C_OwnAddress1 member */
;;;268 I2C_InitStruct->I2C_OwnAddress1 = 0;
000118 8081 STRH r1,[r0,#4]
;;;269
;;;270 /* Initialize the I2C_Ack member */
;;;271 I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
00011a 80c1 STRH r1,[r0,#6]
;;;272
;;;273 /* Initialize the I2C_AcknowledgedAddress member */
;;;274 I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
00011c f44ff44f MOV r1,#0x4000
000120 8101 STRH r1,[r0,#8]
;;;275
;;;276 /* initialize the I2C_ClockSpeed member */
;;;277 I2C_InitStruct->I2C_ClockSpeed = 5000;
000122 f241f241 MOV r1,#0x1388
000126 60c1 STR r1,[r0,#0xc]
;;;278 }
000128 4770 BX lr
;;;279
ENDP
I2C_DMACmd PROC
;;;319
;;;320 if (NewState != DISABLE)
00012a b121 CBZ r1,|L1.310|
;;;321 {
;;;322 /* Enable the selected I2C DMA requests */
;;;323 I2Cx->CR2 |= CR2_DMAEN_Set;
00012c 8881 LDRH r1,[r0,#4]
00012e f441f441 ORR r1,r1,#0x800
000132 8081 STRH r1,[r0,#4]
;;;324 }
;;;325 else
;;;326 {
;;;327 /* Disable the selected I2C DMA requests */
;;;328 I2Cx->CR2 &= CR2_DMAEN_Reset;
;;;329 }
;;;330 }
000134 4770 BX lr
|L1.310|
000136 8881 LDRH r1,[r0,#4]
000138 f421f421 BIC r1,r1,#0x800
00013c 8081 STRH r1,[r0,#4]
00013e 4770 BX lr
;;;331
ENDP
I2C_DMALastTransferCmd PROC
;;;345
;;;346 if (NewState != DISABLE)
000140 b121 CBZ r1,|L1.332|
;;;347 {
;;;348 /* Next DMA end of transfer is the last transfer */
;;;349 I2Cx->CR2 |= CR2_LAST_Set;
000142 8881 LDRH r1,[r0,#4]
000144 f441f441 ORR r1,r1,#0x1000
000148 8081 STRH r1,[r0,#4]
;;;350 }
;;;351 else
;;;352 {
;;;353 /* Next DMA end of transfer is not the last transfer */
;;;354 I2Cx->CR2 &= CR2_LAST_Reset;
;;;355 }
;;;356 }
00014a 4770 BX lr
|L1.332|
00014c 8881 LDRH r1,[r0,#4]
00014e f421f421 BIC r1,r1,#0x1000
000152 8081 STRH r1,[r0,#4]
000154 4770 BX lr
;;;357
ENDP
I2C_GenerateSTART PROC
;;;371
;;;372 if (NewState != DISABLE)
000156 b121 CBZ r1,|L1.354|
;;;373 {
;;;374 /* Generate a START condition */
;;;375 I2Cx->CR1 |= CR1_START_Set;
000158 8801 LDRH r1,[r0,#0]
00015a f441f441 ORR r1,r1,#0x100
00015e 8001 STRH r1,[r0,#0]
;;;376 }
;;;377 else
;;;378 {
;;;379 /* Disable the START condition generation */
;;;380 I2Cx->CR1 &= CR1_START_Reset;
;;;381 }
;;;382 }
000160 4770 BX lr
|L1.354|
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