stm32f10x_i2c.txt
来自「ucos2.86版本结合STM板极支持包」· 文本 代码 · 共 1,102 行 · 第 1/3 页
TXT
1,102 行
000162 8801 LDRH r1,[r0,#0]
000164 f421f421 BIC r1,r1,#0x100
000168 8001 STRH r1,[r0,#0]
00016a 4770 BX lr
;;;383
ENDP
I2C_GenerateSTOP PROC
;;;397
;;;398 if (NewState != DISABLE)
00016c b121 CBZ r1,|L1.376|
;;;399 {
;;;400 /* Generate a STOP condition */
;;;401 I2Cx->CR1 |= CR1_STOP_Set;
00016e 8801 LDRH r1,[r0,#0]
000170 f441f441 ORR r1,r1,#0x200
000174 8001 STRH r1,[r0,#0]
;;;402 }
;;;403 else
;;;404 {
;;;405 /* Disable the STOP condition generation */
;;;406 I2Cx->CR1 &= CR1_STOP_Reset;
;;;407 }
;;;408 }
000176 4770 BX lr
|L1.376|
000178 8801 LDRH r1,[r0,#0]
00017a f421f421 BIC r1,r1,#0x200
00017e 8001 STRH r1,[r0,#0]
000180 4770 BX lr
;;;409
ENDP
I2C_AcknowledgeConfig PROC
;;;423
;;;424 if (NewState != DISABLE)
000182 b121 CBZ r1,|L1.398|
;;;425 {
;;;426 /* Enable the acknowledgement */
;;;427 I2Cx->CR1 |= CR1_ACK_Set;
000184 8801 LDRH r1,[r0,#0]
000186 f441f441 ORR r1,r1,#0x400
00018a 8001 STRH r1,[r0,#0]
;;;428 }
;;;429 else
;;;430 {
;;;431 /* Disable the acknowledgement */
;;;432 I2Cx->CR1 &= CR1_ACK_Reset;
;;;433 }
;;;434 }
00018c 4770 BX lr
|L1.398|
00018e 8801 LDRH r1,[r0,#0]
000190 f421f421 BIC r1,r1,#0x400
000194 8001 STRH r1,[r0,#0]
000196 4770 BX lr
;;;435
ENDP
I2C_OwnAddress2Config PROC
;;;448 /* Get the old register value */
;;;449 tmpreg = I2Cx->OAR2;
000198 8982 LDRH r2,[r0,#0xc]
;;;450 /* Reset I2Cx Own address2 bit [7:1] */
;;;451 tmpreg &= OAR2_ADD2_Reset;
00019a f022f022 BIC r2,r2,#0xfe
;;;452 /* Set I2Cx Own address2 */
;;;453 tmpreg |= (u16)(Address & (u16)0x00FE);
00019e f001f001 AND r1,r1,#0xfe
0001a2 4311 ORRS r1,r1,r2
;;;454 /* Store the new register value */
;;;455 I2Cx->OAR2 = tmpreg;
0001a4 8181 STRH r1,[r0,#0xc]
;;;456 }
0001a6 4770 BX lr
;;;457
ENDP
I2C_DualAddressCmd PROC
;;;471
;;;472 if (NewState != DISABLE)
0001a8 b121 CBZ r1,|L1.436|
;;;473 {
;;;474 /* Enable dual addressing mode */
;;;475 I2Cx->OAR2 |= OAR2_ENDUAL_Set;
0001aa 8981 LDRH r1,[r0,#0xc]
0001ac f041f041 ORR r1,r1,#1
0001b0 8181 STRH r1,[r0,#0xc]
;;;476 }
;;;477 else
;;;478 {
;;;479 /* Disable dual addressing mode */
;;;480 I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
;;;481 }
;;;482 }
0001b2 4770 BX lr
|L1.436|
0001b4 8981 LDRH r1,[r0,#0xc]
0001b6 f021f021 BIC r1,r1,#1
0001ba 8181 STRH r1,[r0,#0xc]
0001bc 4770 BX lr
;;;483
ENDP
I2C_GeneralCallCmd PROC
;;;497
;;;498 if (NewState != DISABLE)
0001be b121 CBZ r1,|L1.458|
;;;499 {
;;;500 /* Enable generall call */
;;;501 I2Cx->CR1 |= CR1_ENGC_Set;
0001c0 8801 LDRH r1,[r0,#0]
0001c2 f041f041 ORR r1,r1,#0x40
0001c6 8001 STRH r1,[r0,#0]
;;;502 }
;;;503 else
;;;504 {
;;;505 /* Disable generall call */
;;;506 I2Cx->CR1 &= CR1_ENGC_Reset;
;;;507 }
;;;508 }
0001c8 4770 BX lr
|L1.458|
0001ca 8801 LDRH r1,[r0,#0]
0001cc f021f021 BIC r1,r1,#0x40
0001d0 8001 STRH r1,[r0,#0]
0001d2 4770 BX lr
;;;509
ENDP
I2C_ITConfig PROC
;;;530
;;;531 if (NewState != DISABLE)
0001d4 b11a CBZ r2,|L1.478|
;;;532 {
;;;533 /* Enable the selected I2C interrupts */
;;;534 I2Cx->CR2 |= I2C_IT;
0001d6 8882 LDRH r2,[r0,#4]
0001d8 4311 ORRS r1,r1,r2
0001da 8081 STRH r1,[r0,#4]
;;;535 }
;;;536 else
;;;537 {
;;;538 /* Disable the selected I2C interrupts */
;;;539 I2Cx->CR2 &= (u16)~I2C_IT;
;;;540 }
;;;541 }
0001dc 4770 BX lr
|L1.478|
0001de 8882 LDRH r2,[r0,#4]
0001e0 ea22ea22 BIC r1,r2,r1
0001e4 8081 STRH r1,[r0,#4]
0001e6 4770 BX lr
;;;542
ENDP
I2C_SendData PROC
;;;553 /* Write in the DR register the data to be sent */
;;;554 I2Cx->DR = Data;
0001e8 8201 STRH r1,[r0,#0x10]
;;;555 }
0001ea 4770 BX lr
;;;556
ENDP
I2C_ReceiveData PROC
;;;566 /* Return the data in the DR register */
;;;567 return (u8)I2Cx->DR;
0001ec 8a00 LDRH r0,[r0,#0x10]
0001ee b2c0 UXTB r0,r0
;;;568 }
0001f0 4770 BX lr
;;;569
ENDP
I2C_Send7bitAddress PROC
;;;588 /* Test on the direction to set/reset the read/write bit */
;;;589 if (I2C_Direction != I2C_Direction_Transmitter)
0001f2 b112 CBZ r2,|L1.506|
;;;590 {
;;;591 /* Set the address ADD0 bit0 for read */
;;;592 Address |= OAR1_ADD0_Set;
0001f4 f041f041 ORR r1,r1,#1
0001f8 e001 B |L1.510|
|L1.506|
;;;593 }
;;;594 else
;;;595 {
;;;596 /* Reset the address bit0 for write */
;;;597 Address &= OAR1_ADD0_Reset;
0001fa f001f001 AND r1,r1,#0xfe
|L1.510|
;;;598 }
;;;599 /* Send the address */
;;;600 I2Cx->DR = Address;
0001fe 8201 STRH r1,[r0,#0x10]
;;;601 }
000200 4770 BX lr
;;;602
ENDP
I2C_ReadRegister PROC
;;;625 /* Return the selected register value */
;;;626 return (*(u16 *)(*((u32 *)&I2Cx) + I2C_Register));
000202 5a40 LDRH r0,[r0,r1]
;;;627 }
000204 4770 BX lr
;;;628
ENDP
I2C_SoftwareResetCmd PROC
;;;642
;;;643 if (NewState != DISABLE)
000206 b121 CBZ r1,|L1.530|
;;;644 {
;;;645 /* Peripheral under reset */
;;;646 I2Cx->CR1 |= CR1_SWRST_Set;
000208 8801 LDRH r1,[r0,#0]
00020a f441f441 ORR r1,r1,#0x8000
00020e 8001 STRH r1,[r0,#0]
;;;647 }
;;;648 else
;;;649 {
;;;650 /* Peripheral not under reset */
;;;651 I2Cx->CR1 &= CR1_SWRST_Reset;
;;;652 }
;;;653 }
000210 4770 BX lr
|L1.530|
000212 8801 LDRH r1,[r0,#0]
000214 f3c1f3c1 UBFX r1,r1,#0,#15
000218 8001 STRH r1,[r0,#0]
00021a 4770 BX lr
;;;654
ENDP
I2C_SMBusAlertConfig PROC
;;;670
;;;671 if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
00021c f5b1f5b1 CMP r1,#0x2000
000220 d104 BNE |L1.556|
;;;672 {
;;;673 /* Drive the SMBusAlert pin Low */
;;;674 I2Cx->CR1 |= I2C_SMBusAlert_Low;
000222 8801 LDRH r1,[r0,#0]
000224 f441f441 ORR r1,r1,#0x2000
000228 8001 STRH r1,[r0,#0]
;;;675 }
;;;676 else
;;;677 {
;;;678 /* Drive the SMBusAlert pin High */
;;;679 I2Cx->CR1 &= I2C_SMBusAlert_High;
;;;680 }
;;;681 }
00022a 4770 BX lr
|L1.556|
00022c 8801 LDRH r1,[r0,#0]
00022e f421f421 BIC r1,r1,#0x3000
000232 8001 STRH r1,[r0,#0]
000234 4770 BX lr
;;;682
ENDP
I2C_TransmitPEC PROC
;;;696
;;;697 if (NewState != DISABLE)
000236 b121 CBZ r1,|L1.578|
;;;698 {
;;;699 /* Enable the selected I2C PEC transmission */
;;;700 I2Cx->CR1 |= CR1_PEC_Set;
000238 8801 LDRH r1,[r0,#0]
00023a f441f441 ORR r1,r1,#0x1000
00023e 8001 STRH r1,[r0,#0]
;;;701 }
;;;702 else
;;;703 {
;;;704 /* Disable the selected I2C PEC transmission */
;;;705 I2Cx->CR1 &= CR1_PEC_Reset;
;;;706 }
;;;707 }
000240 4770 BX lr
|L1.578|
000242 8801 LDRH r1,[r0,#0]
000244 f421f421 BIC r1,r1,#0x1000
000248 8001 STRH r1,[r0,#0]
00024a 4770 BX lr
;;;708
ENDP
I2C_PECPositionConfig PROC
;;;726
;;;727 if (I2C_PECPosition == I2C_PECPosition_Next)
00024c f5b1f5b1 CMP r1,#0x800
000250 d104 BNE |L1.604|
;;;728 {
;;;729 /* PEC indicates that the next byte in shift register is PEC */
;;;730 I2Cx->CR1 |= I2C_PECPosition_Next;
000252 8801 LDRH r1,[r0,#0]
000254 f441f441 ORR r1,r1,#0x800
000258 8001 STRH r1,[r0,#0]
;;;731 }
;;;732 else
;;;733 {
;;;734 /* PEC indicates that the current byte in shift register is PEC */
;;;735 I2Cx->CR1 &= I2C_PECPosition_Current;
;;;736 }
;;;737 }
00025a 4770 BX lr
|L1.604|
00025c 8801 LDRH r1,[r0,#0]
00025e f421f421 BIC r1,r1,#0x800
000262 8001 STRH r1,[r0,#0]
000264 4770 BX lr
;;;738
ENDP
I2C_CalculatePEC PROC
;;;753
;;;754 if (NewState != DISABLE)
000266 b121 CBZ r1,|L1.626|
;;;755 {
;;;756 /* Enable the selected I2C PEC calculation */
;;;757 I2Cx->CR1 |= CR1_ENPEC_Set;
000268 8801 LDRH r1,[r0,#0]
00026a f041f041 ORR r1,r1,#0x20
00026e 8001 STRH r1,[r0,#0]
;;;758 }
;;;759 else
;;;760 {
;;;761 /* Disable the selected I2C PEC calculation */
;;;762 I2Cx->CR1 &= CR1_ENPEC_Reset;
;;;763 }
;;;764 }
000270 4770 BX lr
|L1.626|
000272 8801 LDRH r1,[r0,#0]
000274 f021f021 BIC r1,r1,#0x20
000278 8001 STRH r1,[r0,#0]
00027a 4770 BX lr
;;;765
ENDP
I2C_GetPEC PROC
;;;777 /* Get the PEC value */
;;;778 pec = (I2Cx->SR2) >> 8;
00027c 8b00 LDRH r0,[r0,#0x18]
00027e 0a00 LSRS r0,r0,#8
;;;779 /* Return the selected I2C PEC register value */
;;;780 return pec;
;;;781 }
000280 4770 BX lr
;;;782
ENDP
I2C_ARPCmd PROC
;;;796
;;;797 if (NewState != DISABLE)
000282 b121 CBZ r1,|L1.654|
;;;798 {
;;;799 /* Enable the selected I2C ARP */
;;;800 I2Cx->CR1 |= CR1_ENARP_Set;
000284 8801 LDRH r1,[r0,#0]
000286 f041f041 ORR r1,r1,#0x10
00028a 8001 STRH r1,[r0,#0]
;;;801 }
;;;802 else
;;;803 {
;;;804 /* Disable the selected I2C ARP */
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