pci_top.v

pci pci转local bus总线的应用

// megafunction wizard: %PCI Compiler v4.0.0%
// GENERATION: XML

// ============================================================
// Megafunction Name(s):
// 			pci_t32
// ============================================================
// Generated by PCI Compiler 4.0.0 [Altera, IP Toolbench v1.2.9 build44]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2007 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.


module pci_top (
	clk,
	rstn,
	idsel,
	l_adi,
	lt_rdyn,
	lt_abortn,
	lt_discn,
	lirqn,
	cben,
	framen,
	irdyn,
	intan,
	serrn,
	l_adro,
	l_dato,
	l_beno,
	l_cmdo,
	lt_framen,
	lt_ackn,
	lt_dxfrn,
	lt_tsr,
	cmd_reg,
	stat_reg,
	perrn,
	devseln,
	trdyn,
	stopn,
	ad,
	par);


	input		clk;
	input		rstn;
	input		idsel;
	input	[31:0]	l_adi;
	input		lt_rdyn;
	input		lt_abortn;
	input		lt_discn;
	input		lirqn;
	input	[3:0]	cben;
	input		framen;
	input		irdyn;
	output		intan;
	output		serrn;
	output	[31:0]	l_adro;
	output	[31:0]	l_dato;
	output	[3:0]	l_beno;
	output	[3:0]	l_cmdo;
	output		lt_framen;
	output		lt_ackn;
	output		lt_dxfrn;
	output	[11:0]	lt_tsr;
	output	[6:0]	cmd_reg;
	output	[6:0]	stat_reg;
	output		perrn;
	output		devseln;
	output		trdyn;
	output		stopn;
	inout	[31:0]	ad;
	inout		par;


	pci_t32	pci_t32_inst(
		.clk(clk),
		.rstn(rstn),
		.idsel(idsel),
		.l_adi(l_adi),
		.lt_rdyn(lt_rdyn),
		.lt_abortn(lt_abortn),
		.lt_discn(lt_discn),
		.lirqn(lirqn),
		.cben(cben),
		.framen_in(framen),
		.irdyn_in(irdyn),
		.intan(intan),
		.serrn(serrn),
		.l_adro(l_adro),
		.l_dato(l_dato),
		.l_beno(l_beno),
		.l_cmdo(l_cmdo),
		.lt_framen(lt_framen),
		.lt_ackn(lt_ackn),
		.lt_dxfrn(lt_dxfrn),
		.lt_tsr(lt_tsr),
		.cmd_reg(cmd_reg),
		.stat_reg(stat_reg),
		.perrn(perrn),
		.devseln_out(devseln),
		.trdyn_out(trdyn),
		.stopn_out(stopn),
		.ad(ad),
		.par(par));

	defparam
		pci_t32_inst.CLASS_CODE = 24'hFF0000,
		pci_t32_inst.DEVICE_ID = 16'h0004,
		pci_t32_inst.REVISION_ID = 8'h01,
		pci_t32_inst.SUBSYSTEM_ID = 16'h0000,
		pci_t32_inst.SUBSYSTEM_VENDOR_ID = 16'h0000,
		pci_t32_inst.TARGET_DEVICE = "NEW",
		pci_t32_inst.VENDOR_ID = 16'h1172,
		pci_t32_inst.MIN_GRANT = 8'h00,
		pci_t32_inst.MAX_LATENCY = 8'h00,
		pci_t32_inst.CAP_PTR = 8'h40,
		pci_t32_inst.CIS_PTR = 32'h00000001,
		pci_t32_inst.BAR0 = 32'hFFF00000,
		pci_t32_inst.BAR1 = 32'hFC000000,
		pci_t32_inst.BAR2 = 32'hFFFC0000,
		pci_t32_inst.BAR3 = 32'hFFFC0000,
		pci_t32_inst.BAR4 = 32'hFFF00000,
		pci_t32_inst.BAR5 = 32'hFFF00000,
		pci_t32_inst.NUMBER_OF_BARS = 32'h00000002,
		pci_t32_inst.HARDWIRE_BAR0 = 32'h00000000,
		pci_t32_inst.HARDWIRE_BAR1 = 32'h00000000,
		pci_t32_inst.HARDWIRE_BAR2 = 32'h00000000,
		pci_t32_inst.HARDWIRE_BAR3 = 32'h00000000,
		pci_t32_inst.HARDWIRE_BAR4 = 32'h00000000,
		pci_t32_inst.HARDWIRE_BAR5 = 32'h00000000,
		pci_t32_inst.HARDWIRE_EXP_ROM = 32'h00000001,
		pci_t32_inst.EXP_ROM_BAR = 32'hFFF00000,
		pci_t32_inst.PCI_66MHZ_CAPABLE = "NO",
		pci_t32_inst.INTERRUPT_PIN_REG = 8'h01,
		pci_t32_inst.ENABLE_BITS = 32'h00000000;
endmodule

// =========================================================
// PCI Compiler Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@