sub_tdm.map.rpt

pci pci转local bus总线的应用

Analysis & Synthesis report for sub_tdm
Mon Oct 30 12:03:50 2006
Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst
  6. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg
  7. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_sr:wr_rdn_FF
  8. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_sr:burst_trans
  9. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_sr:tabrt_sig_cyc_reg
 10. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg
 11. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|lpm_compare:bar0_comp
 12. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|lpm_compare:bar1_comp
 13. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|lpm_compare:bar2_comp
 14. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|lpm_compare:bar3_comp
 15. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|pcit32_sr:$00213
 16. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|pcit32_sr:$00216
 17. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|pcit32_sr:$00218
 18. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|pcit32_sr:$00220
 19. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|pcit32_sr:$00222
 20. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|pcit32_sr:$00224
 21. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_pk:parity_Chk
 22. Parameter Settings for User Entity Instance: pci_top:pci|pci_t32:pci_t32_inst|pcit32_pg:parity_gen
 23. Parameter Settings for User Entity Instance: parallel_interface:Parallel_interface
 24. Parameter Settings for User Entity Instance: fpga_misc:misc
 25. Parameter Settings for User Entity Instance: fpga_misc:misc|IIC_SFP:IIC_SFP
 26. Parameter Settings for User Entity Instance: fpga_misc:misc|IIC_RS232:IIC_RS232
 27. Multiplexer Restructuring Statistics (Restructuring Performed)
 28. State Machine - |top|fpga_misc:misc|cstate
 29. State Machine - |top|fpga_misc:misc|IIC_RS232:IIC_RS232|WR_START_STATE
 30. State Machine - |top|fpga_misc:misc|IIC_RS232:IIC_RS232|IIC_WR_STATE
 31. State Machine - |top|fpga_misc:misc|IIC_SFP:IIC_SFP|WR_START_STATE
 32. State Machine - |top|fpga_misc:misc|IIC_SFP:IIC_SFP|IIC_WR_STATE
 33. State Machine - |top|parallel_interface:Parallel_interface|cstate
 34. Partition for Top-Level Resource Utilization by Entity
 35. Analysis & Synthesis Equations
 36. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+-----------------------------+--------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Oct 30 12:03:50 2006            ;
; Quartus II Version          ; 5.0 Build 168 06/22/2005 SP 1.04 SJ Full Version ;
; Revision Name               ; sub_tdm                                          ;
; Top-level Entity Name       ; top                                              ;
; Family                      ; Cyclone                                          ;
; Total logic elements        ; N/A until Partition Merge                        ;
; Total pins                  ; N/A until Partition Merge                        ;
; Total virtual pins          ; N/A until Partition Merge                        ;
; Total memory bits           ; N/A until Partition Merge                        ;
; Total PLLs                  ; N/A until Partition Merge                        ;
+-----------------------------+--------------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C6Q240C8  ;               ;
; Top-level entity name                                              ; top          ; sub_tdm       ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Type of Retiming Performed During Resynthesis                      ; Full         ;               ;
; Resynthesis Optimization Effort                                    ; Normal       ;               ;
; Physical Synthesis Level for Resynthesis                           ; Normal       ;               ;
; Use Generated Physical Constraints File                            ; On           ;               ;
; Use smart compilation                                              ; Off          ; Off           ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; Add Pass-Through Logic to Inferred RAMs                            ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;
; Ignore SOFT Buffers                                                ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off          ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced     ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70           ; 70            ;
; Auto Carry Chains                                                  ; On           ; On            ;
; Auto Open-Drain Pins                                               ; On           ; On            ;
; Remove Duplicate Logic                                             ; On           ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off          ; Off           ;
; Perform gate-level register retiming                               ; Off          ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On           ; On            ;
; Auto ROM Replacement                                               ; On           ; On            ;
; Auto RAM Replacement                                               ; On           ; On            ;
; Auto Shift Register Replacement                                    ; On           ; On            ;