sub_tdm.fit.eqn

pci pci转local bus总线的应用

--D1_dog_rst is RESET_GEN:RESET_GEN|dog_rst at LC_X15_Y16_N6
--operation mode is normal

D1_dog_rst_lut_out = D1L99 & D1L89 & D1L001;
D1_dog_rst = DFFEAS(D1_dog_rst_lut_out, GLOBAL(D1_count[24]), !GLOBAL(D1_dog_reset), , , , , , );


--D1_reset_sof is RESET_GEN:RESET_GEN|reset_sof at LC_X15_Y16_N9
--operation mode is normal

D1_reset_sof = !E1_reset_reg[6] & !D1_dog_rst;


--C1_pi_addr[0] is parallel_interface:Parallel_interface|pi_addr[0] at LC_X21_Y5_N0
--operation mode is normal

C1_pi_addr[0]_lut_out = GND;
C1_pi_addr[0] = DFFEAS(C1_pi_addr[0]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, M1_lt_adr[2], , , VCC);


--C1_pi_addr[1] is parallel_interface:Parallel_interface|pi_addr[1] at LC_X21_Y5_N2
--operation mode is normal

C1_pi_addr[1]_lut_out = M1_lt_adr[3];
C1_pi_addr[1] = DFFEAS(C1_pi_addr[1]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[2] is parallel_interface:Parallel_interface|pi_addr[2] at LC_X21_Y5_N5
--operation mode is normal

C1_pi_addr[2]_lut_out = GND;
C1_pi_addr[2] = DFFEAS(C1_pi_addr[2]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, M1_lt_adr[4], , , VCC);


--C1_pi_addr[3] is parallel_interface:Parallel_interface|pi_addr[3] at LC_X21_Y5_N7
--operation mode is normal

C1_pi_addr[3]_lut_out = M1_lt_adr[5];
C1_pi_addr[3] = DFFEAS(C1_pi_addr[3]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[4] is parallel_interface:Parallel_interface|pi_addr[4] at LC_X12_Y9_N7
--operation mode is normal

C1_pi_addr[4]_lut_out = M1_lt_adr[6];
C1_pi_addr[4] = DFFEAS(C1_pi_addr[4]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[5] is parallel_interface:Parallel_interface|pi_addr[5] at LC_X21_Y5_N8
--operation mode is normal

C1_pi_addr[5]_lut_out = GND;
C1_pi_addr[5] = DFFEAS(C1_pi_addr[5]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, M1_lt_adr[7], , , VCC);


--C1_pi_addr[6] is parallel_interface:Parallel_interface|pi_addr[6] at LC_X21_Y5_N3
--operation mode is normal

C1_pi_addr[6]_lut_out = GND;
C1_pi_addr[6] = DFFEAS(C1_pi_addr[6]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, M1_lt_adr[8], , , VCC);


--C1_pi_addr[7] is parallel_interface:Parallel_interface|pi_addr[7] at LC_X21_Y5_N1
--operation mode is normal

C1_pi_addr[7]_lut_out = GND;
C1_pi_addr[7] = DFFEAS(C1_pi_addr[7]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, M1_lt_adr[9], , , VCC);


--C1_pi_addr[8] is parallel_interface:Parallel_interface|pi_addr[8] at LC_X12_Y9_N4
--operation mode is normal

C1_pi_addr[8]_lut_out = GND;
C1_pi_addr[8] = DFFEAS(C1_pi_addr[8]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, M1_lt_adr[10], , , VCC);


--C1_pi_addr[9] is parallel_interface:Parallel_interface|pi_addr[9] at LC_X11_Y8_N0
--operation mode is normal

C1_pi_addr[9]_lut_out = J1_ad_ir_address[11] & (M1_no_op_reg[3]);
C1_pi_addr[9] = DFFEAS(C1_pi_addr[9]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[10] is parallel_interface:Parallel_interface|pi_addr[10] at LC_X11_Y8_N9
--operation mode is normal

C1_pi_addr[10]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[12];
C1_pi_addr[10] = DFFEAS(C1_pi_addr[10]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[11] is parallel_interface:Parallel_interface|pi_addr[11] at LC_X21_Y5_N6
--operation mode is normal

C1_pi_addr[11]_lut_out = GND;
C1_pi_addr[11] = DFFEAS(C1_pi_addr[11]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, M1_lt_adr[13], , , VCC);


--C1_pi_addr[12] is parallel_interface:Parallel_interface|pi_addr[12] at LC_X21_Y5_N9
--operation mode is normal

C1_pi_addr[12]_lut_out = GND;
C1_pi_addr[12] = DFFEAS(C1_pi_addr[12]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, M1_lt_adr[14], , , VCC);


--C1_pi_addr[13] is parallel_interface:Parallel_interface|pi_addr[13] at LC_X11_Y8_N3
--operation mode is normal

C1_pi_addr[13]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[15];
C1_pi_addr[13] = DFFEAS(C1_pi_addr[13]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[14] is parallel_interface:Parallel_interface|pi_addr[14] at LC_X11_Y8_N5
--operation mode is normal

C1_pi_addr[14]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[16];
C1_pi_addr[14] = DFFEAS(C1_pi_addr[14]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[15] is parallel_interface:Parallel_interface|pi_addr[15] at LC_X21_Y5_N4
--operation mode is normal

C1_pi_addr[15]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[17];
C1_pi_addr[15] = DFFEAS(C1_pi_addr[15]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[16] is parallel_interface:Parallel_interface|pi_addr[16] at LC_X11_Y8_N2
--operation mode is normal

C1_pi_addr[16]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[18];
C1_pi_addr[16] = DFFEAS(C1_pi_addr[16]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[17] is parallel_interface:Parallel_interface|pi_addr[17] at LC_X16_Y3_N4
--operation mode is normal

C1_pi_addr[17]_lut_out = GND;
C1_pi_addr[17] = DFFEAS(C1_pi_addr[17]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, M1_lt_adr[19], , , VCC);


--C1_pi_addr[18] is parallel_interface:Parallel_interface|pi_addr[18] at LC_X11_Y8_N8
--operation mode is normal

C1_pi_addr[18]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[20];
C1_pi_addr[18] = DFFEAS(C1_pi_addr[18]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[19] is parallel_interface:Parallel_interface|pi_addr[19] at LC_X16_Y3_N2
--operation mode is normal

C1_pi_addr[19]_lut_out = J1_ad_ir_address[21] & (M1_no_op_reg[3]);
C1_pi_addr[19] = DFFEAS(C1_pi_addr[19]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[20] is parallel_interface:Parallel_interface|pi_addr[20] at LC_X16_Y3_N5
--operation mode is normal

C1_pi_addr[20]_lut_out = J1_ad_ir_address[22] & M1_no_op_reg[3];
C1_pi_addr[20] = DFFEAS(C1_pi_addr[20]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--C1_pi_addr[21] is parallel_interface:Parallel_interface|pi_addr[21] at LC_X11_Y8_N1
--operation mode is normal

C1_pi_addr[21]_lut_out = M1_no_op_reg[3] & J1_ad_ir_address[23];
C1_pi_addr[21] = DFFEAS(C1_pi_addr[21]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L054, , , , );


--M1_TS_IDLE_NOT is pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|TS_IDLE_NOT at LC_X13_Y7_N8
--operation mode is normal

M1_TS_IDLE_NOT = AMPP_FUNCTION(pci_clk, M1_TS_IDLE_d_lc, M1_TS_IDLE_d_lc1, P1L381, reset_n);


--P1_bar_hitR[3] is pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|bar_hitR[3] at LC_X14_Y6_N8
--operation mode is normal

P1_bar_hitR[3] = AMPP_FUNCTION(pci_clk, P1_bar_hit[3], M1_bar_hit_rst, P1_bar_hitR[3], reset_n);


--P1_bar_hitR[1] is pci_top:pci|pci_t32:pci_t32_inst|pcit32_t:trg|pcit32_c:cfg|bar_hitR[1] at LC_X13_Y7_N5
--operation mode is normal

P1_bar_hitR[1] = AMPP_FUNCTION(pci_clk, P1_bar_hit[1], P1_bar_hitR[1], M1_bar_hit_rst, reset_n);


--C1L202 is parallel_interface:Parallel_interface|reduce_nor~1 at LC_X16_Y6_N1
--operation mode is normal

C1L202 = J1_cben_ir_address[3] # J1_cben_ir_address[0] # !J1_cben_ir_address[2] # !J1_cben_ir_address[1];


--C1L301 is parallel_interface:Parallel_interface|dir~42 at LC_X14_Y7_N6
--operation mode is normal

C1L301 = M1_TS_IDLE_NOT & !C1L202 & (P1_bar_hitR[3] # P1_bar_hitR[1]);


--C1_cpu_cs_n is parallel_interface:Parallel_interface|cpu_cs_n at LC_X20_Y6_N0
--operation mode is normal

C1_cpu_cs_n_lut_out = !C1L1 & !C1L3 & (C1_cstate.IDLE # !C1L5);
C1_cpu_cs_n = DFFEAS(C1_cpu_cs_n_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , , , , , );


--C1_cpu_oe_n is parallel_interface:Parallel_interface|cpu_oe_n at LC_X20_Y6_N5
--operation mode is normal

C1_cpu_oe_n_lut_out = !C1L1 & !C1L6 & (!C1L9 # !C1L8);
C1_cpu_oe_n = DFFEAS(C1_cpu_oe_n_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , , , , , );


--C1_cpu_we_n is parallel_interface:Parallel_interface|cpu_we_n at LC_X20_Y5_N9
--operation mode is normal

C1_cpu_we_n_lut_out = !C1_cstate.WRITE_ZAR_3 & !C1L01 & (C1_cstate.IDLE # !C1L21);
C1_cpu_we_n = DFFEAS(C1_cpu_we_n_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , , , , , );


--C1_cpu_ts_ale is parallel_interface:Parallel_interface|cpu_ts_ale at LC_X20_Y5_N5
--operation mode is normal

C1_cpu_ts_ale_lut_out = C1L31 # C1L4 & C1L41 # !C1L51;
C1_cpu_ts_ale = DFFEAS(C1_cpu_ts_ale_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , , , , , );


--E1_led_reg[2] is fpga_misc:misc|led_reg[2] at LC_X14_Y9_N8
--operation mode is normal

E1_led_reg[2]_lut_out = !J1_low_ad_IR_data[2];
E1_led_reg[2] = DFFEAS(E1_led_reg[2]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L403, , , , );


--E1_led_reg[1] is fpga_misc:misc|led_reg[1] at LC_X10_Y10_N4
--operation mode is normal

E1_led_reg[1]_lut_out = !J1_low_ad_IR_data[1];
E1_led_reg[1] = DFFEAS(E1_led_reg[1]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L403, , , , );


--E1_led_reg[0] is fpga_misc:misc|led_reg[0] at LC_X10_Y10_N5
--operation mode is normal

E1_led_reg[0]_lut_out = !J1_low_ad_IR_data[0];
E1_led_reg[0] = DFFEAS(E1_led_reg[0]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L403, , , , );


--B1L92 is INT_LED:INT_LED|run_led~8 at LC_X10_Y10_N7
--operation mode is normal

B1L92 = E1_led_reg[0] & (D1_count[22]) # !E1_led_reg[0] & D1_count[24];


--E1_int_mask[2] is fpga_misc:misc|int_mask[2] at LC_X13_Y17_N2
--operation mode is normal

E1_int_mask[2]_lut_out = !J1_low_ad_IR_data[2];
E1_int_mask[2] = DFFEAS(E1_int_mask[2]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L482, , , , );


--E1_int_mask[8] is fpga_misc:misc|int_mask[8] at LC_X14_Y17_N5
--operation mode is normal

E1_int_mask[8]_lut_out = !J1_low_ad_IR_data[8];
E1_int_mask[8] = DFFEAS(E1_int_mask[8]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L482, , , , );


--B1L71 is INT_LED:INT_LED|fpga_int~51 at LC_X14_Y17_N1
--operation mode is normal

B1L71 = bcm5464_int_n[3] & !E1_int_mask[8] & (bcm5248_int[1] # !E1_int_mask[2]) # !bcm5464_int_n[3] & (bcm5248_int[1] # !E1_int_mask[2]);


--E1_int_mask[1] is fpga_misc:misc|int_mask[1] at LC_X13_Y17_N8
--operation mode is normal

E1_int_mask[1]_lut_out = !J1_low_ad_IR_data[1];
E1_int_mask[1] = DFFEAS(E1_int_mask[1]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L482, , , , );


--B1_bcm5248_int0 is INT_LED:INT_LED|bcm5248_int0 at LC_X13_Y15_N2
--operation mode is normal

B1_bcm5248_int0 = E1_int_mask[1] & !bcm5248_int[0];


--E1_int_mask[6] is fpga_misc:misc|int_mask[6] at LC_X12_Y16_N8
--operation mode is normal

E1_int_mask[6]_lut_out = !J1_low_ad_IR_data[6];
E1_int_mask[6] = DFFEAS(E1_int_mask[6]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L482, , , , );


--B1_bcm5464_int1 is INT_LED:INT_LED|bcm5464_int1 at LC_X14_Y16_N1
--operation mode is normal

B1_bcm5464_int1 = bcm5464_int_n[1] & E1_int_mask[6];


--E1_int_mask[4] is fpga_misc:misc|int_mask[4] at LC_X14_Y17_N6
--operation mode is normal

E1_int_mask[4]_lut_out = !J1_low_ad_IR_data[4];
E1_int_mask[4] = DFFEAS(E1_int_mask[4]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L482, , , , );


--B1_bcm5248_int3 is INT_LED:INT_LED|bcm5248_int3 at LC_X14_Y17_N8
--operation mode is normal

B1_bcm5248_int3 = !bcm5248_int[3] & E1_int_mask[4];


--E1_int_mask[5] is fpga_misc:misc|int_mask[5] at LC_X13_Y13_N7
--operation mode is normal

E1_int_mask[5]_lut_out = !J1_low_ad_IR_data[5];
E1_int_mask[5] = DFFEAS(E1_int_mask[5]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L482, , , , );


--B1_bcm5464_int0 is INT_LED:INT_LED|bcm5464_int0 at LC_X13_Y13_N5
--operation mode is normal

B1_bcm5464_int0 = E1_int_mask[5] & bcm5464_int_n[0];


--E1_int_mask[7] is fpga_misc:misc|int_mask[7] at LC_X12_Y16_N2
--operation mode is normal

E1_int_mask[7]_lut_out = !J1_low_ad_IR_data[7];
E1_int_mask[7] = DFFEAS(E1_int_mask[7]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L482, , , , );


--B1_bcm5464_int2 is INT_LED:INT_LED|bcm5464_int2 at LC_X13_Y16_N6
--operation mode is normal

B1_bcm5464_int2 = bcm5464_int_n[2] & E1_int_mask[7];


--E1_int_mask[3] is fpga_misc:misc|int_mask[3] at LC_X13_Y17_N0
--operation mode is normal

E1_int_mask[3]_lut_out = !J1_low_ad_IR_data[3];
E1_int_mask[3] = DFFEAS(E1_int_mask[3]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L482, , , , );


--B1_bcm5248_int2 is INT_LED:INT_LED|bcm5248_int2 at LC_X13_Y17_N6
--operation mode is normal

B1_bcm5248_int2 = !bcm5248_int[2] & E1_int_mask[3];


--B1L81 is INT_LED:INT_LED|fpga_int~52 at LC_X14_Y17_N3
--operation mode is normal

B1L81 = !B1_bcm5464_int2 & !B1_bcm5464_int0 & !B1_bcm5248_int3 & !B1_bcm5248_int2;


--B1L91 is INT_LED:INT_LED|fpga_int~53 at LC_