sub_tdm.fit.eqn

pci pci转local bus总线的应用

D1_count[7]_carry_eqn = D1L02;
D1_count[7]_lut_out = D1_count[7] $ D1_count[7]_carry_eqn;
D1_count[7] = DFFEAS(D1_count[7]_lut_out, GLOBAL(pci_clk), VCC, , , , , , );

--D1L22 is RESET_GEN:RESET_GEN|count[7]~244 at LC_X9_Y11_N0
--operation mode is arithmetic

D1L22_cout_0 = !D1L02 # !D1_count[7];
D1L22 = CARRY(D1L22_cout_0);

--D1L32 is RESET_GEN:RESET_GEN|count[7]~244COUT1_281 at LC_X9_Y11_N0
--operation mode is arithmetic

D1L32_cout_1 = !D1L02 # !D1_count[7];
D1L32 = CARRY(D1L32_cout_1);


--D1_count[6] is RESET_GEN:RESET_GEN|count[6] at LC_X9_Y12_N9
--operation mode is arithmetic

D1_count[6]_carry_eqn = (!D1L6 & D1L71) # (D1L6 & D1L81);
D1_count[6]_lut_out = D1_count[6] $ (!D1_count[6]_carry_eqn);
D1_count[6] = DFFEAS(D1_count[6]_lut_out, GLOBAL(pci_clk), VCC, , , , , , );

--D1L02 is RESET_GEN:RESET_GEN|count[6]~248 at LC_X9_Y12_N9
--operation mode is arithmetic

D1L02 = CARRY(D1_count[6] & (!D1L81));


--D1_count[5] is RESET_GEN:RESET_GEN|count[5] at LC_X9_Y12_N8
--operation mode is arithmetic

D1_count[5]_carry_eqn = (!D1L6 & D1L41) # (D1L6 & D1L51);
D1_count[5]_lut_out = D1_count[5] $ D1_count[5]_carry_eqn;
D1_count[5] = DFFEAS(D1_count[5]_lut_out, GLOBAL(pci_clk), VCC, , , , , , );

--D1L71 is RESET_GEN:RESET_GEN|count[5]~252 at LC_X9_Y12_N8
--operation mode is arithmetic

D1L71_cout_0 = !D1L41 # !D1_count[5];
D1L71 = CARRY(D1L71_cout_0);

--D1L81 is RESET_GEN:RESET_GEN|count[5]~252COUT1_280 at LC_X9_Y12_N8
--operation mode is arithmetic

D1L81_cout_1 = !D1L51 # !D1_count[5];
D1L81 = CARRY(D1L81_cout_1);


--D1_count[4] is RESET_GEN:RESET_GEN|count[4] at LC_X9_Y12_N7
--operation mode is arithmetic

D1_count[4]_carry_eqn = (!D1L6 & D1L11) # (D1L6 & D1L21);
D1_count[4]_lut_out = D1_count[4] $ (!D1_count[4]_carry_eqn);
D1_count[4] = DFFEAS(D1_count[4]_lut_out, GLOBAL(pci_clk), VCC, , , , , , );

--D1L41 is RESET_GEN:RESET_GEN|count[4]~256 at LC_X9_Y12_N7
--operation mode is arithmetic

D1L41_cout_0 = D1_count[4] & (!D1L11);
D1L41 = CARRY(D1L41_cout_0);

--D1L51 is RESET_GEN:RESET_GEN|count[4]~256COUT1_279 at LC_X9_Y12_N7
--operation mode is arithmetic

D1L51_cout_1 = D1_count[4] & (!D1L21);
D1L51 = CARRY(D1L51_cout_1);


--D1_count[3] is RESET_GEN:RESET_GEN|count[3] at LC_X9_Y12_N6
--operation mode is arithmetic

D1_count[3]_carry_eqn = (!D1L6 & D1L8) # (D1L6 & D1L9);
D1_count[3]_lut_out = D1_count[3] $ (D1_count[3]_carry_eqn);
D1_count[3] = DFFEAS(D1_count[3]_lut_out, GLOBAL(pci_clk), VCC, , , , , , );

--D1L11 is RESET_GEN:RESET_GEN|count[3]~260 at LC_X9_Y12_N6
--operation mode is arithmetic

D1L11_cout_0 = !D1L8 # !D1_count[3];
D1L11 = CARRY(D1L11_cout_0);

--D1L21 is RESET_GEN:RESET_GEN|count[3]~260COUT1_278 at LC_X9_Y12_N6
--operation mode is arithmetic

D1L21_cout_1 = !D1L9 # !D1_count[3];
D1L21 = CARRY(D1L21_cout_1);


--D1_count[2] is RESET_GEN:RESET_GEN|count[2] at LC_X9_Y12_N5
--operation mode is arithmetic

D1_count[2]_carry_eqn = D1L6;
D1_count[2]_lut_out = D1_count[2] $ !D1_count[2]_carry_eqn;
D1_count[2] = DFFEAS(D1_count[2]_lut_out, GLOBAL(pci_clk), VCC, , , , , , );

--D1L8 is RESET_GEN:RESET_GEN|count[2]~264 at LC_X9_Y12_N5
--operation mode is arithmetic

D1L8_cout_0 = D1_count[2] & !D1L6;
D1L8 = CARRY(D1L8_cout_0);

--D1L9 is RESET_GEN:RESET_GEN|count[2]~264COUT1_277 at LC_X9_Y12_N5
--operation mode is arithmetic

D1L9_cout_1 = D1_count[2] & !D1L6;
D1L9 = CARRY(D1L9_cout_1);


--D1_count[1] is RESET_GEN:RESET_GEN|count[1] at LC_X9_Y12_N4
--operation mode is arithmetic

D1_count[1]_lut_out = D1_count[1] $ D1L3;
D1_count[1] = DFFEAS(D1_count[1]_lut_out, GLOBAL(pci_clk), VCC, , , , , , );

--D1L6 is RESET_GEN:RESET_GEN|count[1]~268 at LC_X9_Y12_N4
--operation mode is arithmetic

D1L6 = CARRY(!D1L4 # !D1_count[1]);


--D1_count[0] is RESET_GEN:RESET_GEN|count[0] at LC_X9_Y12_N3
--operation mode is arithmetic

D1_count[0]_lut_out = !D1_count[0];
D1_count[0] = DFFEAS(D1_count[0]_lut_out, GLOBAL(pci_clk), VCC, , , , , , );

--D1L3 is RESET_GEN:RESET_GEN|count[0]~272 at LC_X9_Y12_N3
--operation mode is arithmetic

D1L3_cout_0 = D1_count[0];
D1L3 = CARRY(D1L3_cout_0);

--D1L4 is RESET_GEN:RESET_GEN|count[0]~272COUT1_276 at LC_X9_Y12_N3
--operation mode is arithmetic

D1L4_cout_1 = D1_count[0];
D1L4 = CARRY(D1L4_cout_1);


--H1_W_DATA_BUF[22] is fpga_misc:misc|IIC_SFP:IIC_SFP|W_DATA_BUF[22] at LC_X11_Y11_N7
--operation mode is normal

H1_W_DATA_BUF[22]_lut_out = E1_SFPIIC_DATA_IN[7] # !E1_SFPIIC_W_R;
H1_W_DATA_BUF[22] = DFFEAS(H1_W_DATA_BUF[22]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , H1L37, H1_W_DATA_BUF[21], , , H1_IIC_WR_STATE.WRITE_READ);


--G1_W_DATA_BUF[22] is fpga_misc:misc|IIC_RS232:IIC_RS232|W_DATA_BUF[22] at LC_X15_Y14_N0
--operation mode is normal

G1_W_DATA_BUF[22]_lut_out = E1_IIC_DATA_IN[7] # !E1_IIC_W_R;
G1_W_DATA_BUF[22] = DFFEAS(G1_W_DATA_BUF[22]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , G1L79, G1_W_DATA_BUF[21], , , G1_IIC_WR_STATE.WRITE_READ);


--H1_W_DATA_BUF[21] is fpga_misc:misc|IIC_SFP:IIC_SFP|W_DATA_BUF[21] at LC_X11_Y11_N2
--operation mode is normal

H1_W_DATA_BUF[21]_lut_out = E1_SFPIIC_W_R & (E1_SFPIIC_DATA_IN[6]);
H1_W_DATA_BUF[21] = DFFEAS(H1_W_DATA_BUF[21]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , H1L37, H1_W_DATA_BUF[20], , , H1_IIC_WR_STATE.WRITE_READ);


--G1_W_DATA_BUF[21] is fpga_misc:misc|IIC_RS232:IIC_RS232|W_DATA_BUF[21] at LC_X15_Y14_N5
--operation mode is normal

G1_W_DATA_BUF[21]_lut_out = E1_IIC_W_R & (E1_IIC_DATA_IN[6]);
G1_W_DATA_BUF[21] = DFFEAS(G1_W_DATA_BUF[21]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , G1L79, G1_W_DATA_BUF[20], , , G1_IIC_WR_STATE.WRITE_READ);


--H1_W_DATA_BUF[20] is fpga_misc:misc|IIC_SFP:IIC_SFP|W_DATA_BUF[20] at LC_X11_Y11_N9
--operation mode is normal

H1_W_DATA_BUF[20]_lut_out = E1_SFPIIC_W_R & (E1_SFPIIC_DATA_IN[5]) # !E1_SFPIIC_W_R & !E1_SFPSLAVE_ADDR[6];
H1_W_DATA_BUF[20] = DFFEAS(H1_W_DATA_BUF[20]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , H1L37, H1_W_DATA_BUF[19], , , H1_IIC_WR_STATE.WRITE_READ);


--G1_W_DATA_BUF[20] is fpga_misc:misc|IIC_RS232:IIC_RS232|W_DATA_BUF[20] at LC_X15_Y14_N8
--operation mode is normal

G1_W_DATA_BUF[20]_lut_out = E1_IIC_DATA_IN[5] # !E1_IIC_W_R;
G1_W_DATA_BUF[20] = DFFEAS(G1_W_DATA_BUF[20]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , G1L79, G1_W_DATA_BUF[19], , , G1_IIC_WR_STATE.WRITE_READ);


--H1_W_DATA_BUF[19] is fpga_misc:misc|IIC_SFP:IIC_SFP|W_DATA_BUF[19] at LC_X10_Y13_N4
--operation mode is normal

H1_W_DATA_BUF[19]_lut_out = E1_SFPIIC_W_R & (E1_SFPIIC_DATA_IN[4]) # !E1_SFPIIC_W_R & E1_SFPSLAVE_ADDR[5];
H1_W_DATA_BUF[19] = DFFEAS(H1_W_DATA_BUF[19]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , H1L37, H1_W_DATA_BUF[18], , , H1_IIC_WR_STATE.WRITE_READ);


--G1_W_DATA_BUF[19] is fpga_misc:misc|IIC_RS232:IIC_RS232|W_DATA_BUF[19] at LC_X15_Y14_N9
--operation mode is normal

G1_W_DATA_BUF[19]_lut_out = E1_IIC_W_R & (E1_IIC_DATA_IN[4]);
G1_W_DATA_BUF[19] = DFFEAS(G1_W_DATA_BUF[19]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , G1L79, G1_W_DATA_BUF[18], , , G1_IIC_WR_STATE.WRITE_READ);


--H1_W_DATA_BUF[18] is fpga_misc:misc|IIC_SFP:IIC_SFP|W_DATA_BUF[18] at LC_X10_Y13_N9
--operation mode is normal

H1_W_DATA_BUF[18]_lut_out = E1_SFPIIC_W_R & (E1_SFPIIC_DATA_IN[3]) # !E1_SFPIIC_W_R & !E1_SFPSLAVE_ADDR[4];
H1_W_DATA_BUF[18] = DFFEAS(H1_W_DATA_BUF[18]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , H1L37, H1_W_DATA_BUF[17], , , H1_IIC_WR_STATE.WRITE_READ);


--G1_W_DATA_BUF[18] is fpga_misc:misc|IIC_RS232:IIC_RS232|W_DATA_BUF[18] at LC_X15_Y14_N2
--operation mode is normal

G1_W_DATA_BUF[18]_lut_out = E1_IIC_DATA_IN[3] # !E1_IIC_W_R;
G1_W_DATA_BUF[18] = DFFEAS(G1_W_DATA_BUF[18]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , G1L79, G1_W_DATA_BUF[17], , , G1_IIC_WR_STATE.WRITE_READ);


--H1_W_DATA_BUF[17] is fpga_misc:misc|IIC_SFP:IIC_SFP|W_DATA_BUF[17] at LC_X10_Y13_N2
--operation mode is normal

H1_W_DATA_BUF[17]_lut_out = E1_SFPIIC_W_R & (E1_SFPIIC_DATA_IN[2]) # !E1_SFPIIC_W_R & E1_SFPSLAVE_ADDR[3];
H1_W_DATA_BUF[17] = DFFEAS(H1_W_DATA_BUF[17]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , H1L37, H1_W_DATA_BUF[16], , , H1_IIC_WR_STATE.WRITE_READ);


--G1_W_DATA_BUF[17] is fpga_misc:misc|IIC_RS232:IIC_RS232|W_DATA_BUF[17] at LC_X15_Y14_N6
--operation mode is normal

G1_W_DATA_BUF[17]_lut_out = E1_IIC_W_R & (E1_IIC_DATA_IN[2]);
G1_W_DATA_BUF[17] = DFFEAS(G1_W_DATA_BUF[17]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , G1L79, G1_W_DATA_BUF[16], , , G1_IIC_WR_STATE.WRITE_READ);


--H1_W_DATA_BUF[16] is fpga_misc:misc|IIC_SFP:IIC_SFP|W_DATA_BUF[16] at LC_X10_Y13_N8
--operation mode is normal

H1_W_DATA_BUF[16]_lut_out = E1_SFPIIC_W_R & E1_SFPIIC_DATA_IN[1] # !E1_SFPIIC_W_R & (!E1_SFPSLAVE_ADDR[2]);
H1_W_DATA_BUF[16] = DFFEAS(H1_W_DATA_BUF[16]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , H1L37, H1_W_DATA_BUF[15], , , H1_IIC_WR_STATE.WRITE_READ);


--G1_W_DATA_BUF[16] is fpga_misc:misc|IIC_RS232:IIC_RS232|W_DATA_BUF[16] at LC_X15_Y14_N4
--operation mode is normal

G1_W_DATA_BUF[16]_lut_out = E1_IIC_DATA_IN[1] # !E1_IIC_W_R;
G1_W_DATA_BUF[16] = DFFEAS(G1_W_DATA_BUF[16]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , G1L79, G1_W_DATA_BUF[15], , , G1_IIC_WR_STATE.WRITE_READ);


--H1_W_DATA_BUF[15] is fpga_misc:misc|IIC_SFP:IIC_SFP|W_DATA_BUF[15] at LC_X10_Y13_N7
--operation mode is normal

H1_W_DATA_BUF[15]_lut_out = E1_SFPIIC_W_R & (E1_SFPIIC_DATA_IN[0]) # !E1_SFPIIC_W_R & !E1_SFPSLAVE_ADDR[1];
H1_W_DATA_BUF[15] = DFFEAS(H1_W_DATA_BUF[15]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , H1L37, H1_W_DATA_BUF[14], , , H1_IIC_WR_STATE.WRITE_READ);


--G1_W_DATA_BUF[15] is fpga_misc:misc|IIC_RS232:IIC_RS232|W_DATA_BUF[15] at LC_X15_Y14_N7
--operation mode is normal

G1_W_DATA_BUF[15]_lut_out = E1_IIC_W_R & (E1_IIC_DATA_IN[0]);
G1_W_DATA_BUF[15] = DFFEAS(G1_W_DATA_BUF[15]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , G1L79, G1_W_DATA_BUF[14], , , G1_IIC_WR_STATE.WRITE_READ);


--H1_W_DATA_BUF[14] is fpga_misc:misc|IIC_SFP:IIC_SFP|W_DATA_BUF[14] at LC_X10_Y14_N2
--operation mode is normal

H1_W_DATA_BUF[14]_lut_out = E1_SFPSLAVE_ADDR[0] & (!E1_SFPIIC_W_R);
H1_W_DATA_BUF[14] = DFFEAS(H1_W_DATA_BUF[14]_lut_out, GLOBAL(G1_CLK_COUNT[7]), GLOBAL(reset_n), , H1L82, H1_W_DATA_BUF[13], , , H1_IIC_WR_STATE.WRITE_READ);


--H1_WR_FLAG is fpga_misc:misc|IIC_SFP:IIC_SFP|WR_FLAG at LC_X11_Y17_N6
--operation mode is normal

H1_WR_FLAG_lut_out = H1L25 & !H1L15 & (H1_WR_COUNT[3] # !H1L65) # !H1L25 & (H1_WR_COUNT[3] # !H1L65);
H1_WR_FLAG = DFFEAS(H1_WR_FLAG_lut_out, !GLOBAL(G1_CLK_COUNT[8]), GLOBAL(reset_n), , , , , , );


--E1_SFP_ADDRESS[0] is fpga_misc:misc|SFP_ADDRESS[0] at LC_X13_Y16_N2
--operation mode is normal

E1_SFP_ADDRESS[0]_lut_out = J1_low_ad_IR_data[4];
E1_SFP_ADDRESS[0] = DFFEAS(E1_SFP_ADDRESS[0]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L25, , , , );


--E1_reset_reg[0] is fpga_misc:misc|reset_reg[0] at LC_X12_Y14_N6
--operation mode is normal

E1_reset_reg[0]_lut_out = !J1_low_ad_IR_data[0];
E1_reset_reg[0] = DFFEAS(E1_reset_reg[0]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L963, , , , );


--D1_reset_8245 is RESET_GEN:RESET_GEN|reset_8245 at LC_X10_Y19_N2
--operation mode is normal

D1_reset_8245 = reset_n & (!E1_reset_reg[0]);


--E1_reset_reg[3] is fpga_misc:misc|reset_reg[3] at LC_X12_Y14_N0
--operation mode is normal

E1_reset_reg[3]_lut_out = !J1_low_ad_IR_data[3];
E1_reset_reg[3] = DFFEAS(E1_reset_reg[3]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L963, , , , );


--D1_reset_5248 is RESET_GEN:RESET_GEN|reset_5248 at LC_X12_Y18_N2
--operation mode is normal

D1_reset_5248 = !E1_reset_reg[3] & reset_n;


--E1_reset_reg[1] is fpga_misc:misc|reset_reg[1] at LC_X12_Y14_N5
--operation mode is normal

E1_reset_reg[1]_lut_out = !J1_low_ad_IR_data[1];
E1_reset_reg[1] = DFFEAS(E1_reset_reg[1]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L963, , , , );


--D1_reset_5650 is RESET_GEN:RESET_GEN|reset_5650 at LC_X13_Y17_N9
--operation mode is normal

D1_reset_5650 = !E1_reset_reg[1] & (reset_n);


--E1_reset_reg[2] is fpga_misc:misc|reset_reg[2] at LC_X12_Y14_N7
--operation mode is normal

E1_reset_reg[2]_lut_out = !J1_low_ad_IR_data[2];
E1_reset_reg[2] = DFFEAS(E1_reset_reg[2]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L963, , , , );


--D1_reset_5464 is RESET_GEN:RESET_GEN|reset_5464 at LC_X10_Y20_N2
--operation mode is normal

D1_reset_5464 = !E1_reset_reg[2] & reset_n;


--E1_reset_reg[4] is fpga_misc:misc|reset_reg[4] at LC_X12_Y14_N3
--operation mode is normal

E1_reset_reg[4]_lut_out = !J1_low_ad_IR_data[4];
E1_reset_reg[4] = DFFEAS(E1_reset_reg[4]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L963, , , , );


--D1_reset_rs232 is RESET_GEN:RESET_GEN|reset_rs232 at LC_X26_Y13_N2
--operation mode is normal

D1_reset_rs232 = !E1_reset_reg[4] & reset_n;


--E1_reset_reg[5] is fpga_misc:misc|reset_reg[5] at LC_X12_Y14_N8
--operation mode is normal

E1_reset_reg[5]_lut_out = !J1_low_ad_IR_data[5];
E1_reset_reg[5] = DFFEAS(E1_reset_reg[5]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L963, , , , );


--D1_reset_zl is RESET_GEN:RESET_GEN|reset_zl at LC_X12_Y12_N7
--operation mode is normal

D1_reset_zl = reset_n & (!E1_reset_reg[5]);


--E1_reset_reg[6] is fpga_misc:misc|reset_reg[6] at LC_X10_Y12_N2
--operation mode is normal

E1_reset_reg[6]_lut_out = VCC;
E1_reset_reg[6] = DFFEAS(E1_reset_reg[6]_lut_out, GLOBAL(pci_clk), GLOBAL(reset_n), , E1L973, , , , );