golomb2.tan.qmsg

golomb编码

{ "Info" "ITDB_TSU_RESULT" "err\[1\] wen clkx10 5.780 ns register " "Info: tsu for register \"err\[1\]\" (data pin = \"wen\", clock pin = \"clkx10\") is 5.780 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.646 ns + Longest pin register " "Info: + Longest pin to register delay is 8.646 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns wen 1 PIN PIN_78 32 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_78; Fanout = 32; PIN Node = 'wen'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { wen } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.304 ns) + CELL(0.867 ns) 8.646 ns err\[1\] 2 REG LC_X13_Y8_N8 1 " "Info: 2: + IC(6.304 ns) + CELL(0.867 ns) = 8.646 ns; Loc. = LC_X13_Y8_N8; Fanout = 1; REG Node = 'err\[1\]'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "7.171 ns" { wen err[1] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns 27.09 % " "Info: Total cell delay = 2.342 ns ( 27.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.304 ns 72.91 % " "Info: Total interconnect delay = 6.304 ns ( 72.91 % )" {  } {  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "8.646 ns" { wen err[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "8.646 ns" { wen wen~out0 err[1] } { 0.000ns 0.000ns 6.304ns } { 0.000ns 1.475ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx10 destination 2.903 ns - Shortest register " "Info: - Shortest clock path from clock \"clkx10\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx10 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clkx10'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { clkx10 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns err\[1\] 2 REG LC_X13_Y8_N8 1 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X13_Y8_N8; Fanout = 1; REG Node = 'err\[1\]'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.434 ns" { clkx10 err[1] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 err[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 err[1] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "8.646 ns" { wen err[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "8.646 ns" { wen wen~out0 err[1] } { 0.000ns 0.000ns 6.304ns } { 0.000ns 1.475ns 0.867ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 err[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 err[1] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkx8 dataout\[21\] dataout\[21\]~reg0 8.213 ns register " "Info: tco from clock \"clkx8\" to destination pin \"dataout\[21\]\" through register \"dataout\[21\]~reg0\" is 8.213 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx8 source 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clkx8\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx8 1 CLK PIN_29 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 50; CLK Node = 'clkx8'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { clkx8 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns dataout\[21\]~reg0 2 REG LC_X12_Y10_N5 1 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X12_Y10_N5; Fanout = 1; REG Node = 'dataout\[21\]~reg0'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.456 ns" { clkx8 dataout[21]~reg0 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 230 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 dataout[21]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 dataout[21]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 230 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.064 ns + Longest register pin " "Info: + Longest register to pin delay is 5.064 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dataout\[21\]~reg0 1 REG LC_X12_Y10_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N5; Fanout = 1; REG Node = 'dataout\[21\]~reg0'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { dataout[21]~reg0 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 230 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.940 ns) + CELL(2.124 ns) 5.064 ns dataout\[21\] 2 PIN PIN_21 0 " "Info: 2: + IC(2.940 ns) + CELL(2.124 ns) = 5.064 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'dataout\[21\]'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "5.064 ns" { dataout[21]~reg0 dataout[21] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 41.94 % " "Info: Total cell delay = 2.124 ns ( 41.94 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.940 ns 58.06 % " "Info: Total interconnect delay = 2.940 ns ( 58.06 % )" {  } {  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "5.064 ns" { dataout[21]~reg0 dataout[21] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.064 ns" { dataout[21]~reg0 dataout[21] } { 0.000ns 2.940ns } { 0.000ns 2.124ns } } }  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 dataout[21]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925