📄 golomb2.tan.qmsg
字号:
{ "Info" "ITDB_FULL_SLACK_RESULT" "clkx10 register js\[2\] register js\[3\] 6.761 ns " "Info: Slack time is 6.761 ns for clock \"clkx10\" between source register \"js\[2\]\" and destination register \"js\[3\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" { } { } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.739 ns + Largest register register " "Info: + Largest register to register requirement is 9.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clkx10 10.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clkx10\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clkx10 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clkx10\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx10 destination 2.903 ns + Shortest register " "Info: + Shortest clock path from clock \"clkx10\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx10 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clkx10'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { clkx10 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns js\[3\] 2 REG LC_X12_Y7_N4 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X12_Y7_N4; Fanout = 4; REG Node = 'js\[3\]'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.434 ns" { clkx10 js[3] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" { } { } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[3] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx10 source 2.903 ns - Longest register " "Info: - Longest clock path from clock \"clkx10\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx10 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clkx10'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { clkx10 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns js\[2\] 2 REG LC_X12_Y7_N5 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X12_Y7_N5; Fanout = 4; REG Node = 'js\[2\]'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.434 ns" { clkx10 js[2] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" { } { } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[2] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[3] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[2] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[3] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[2] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.978 ns - Longest register register " "Info: - Longest register to register delay is 2.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns js\[2\] 1 REG LC_X12_Y7_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y7_N5; Fanout = 4; REG Node = 'js\[2\]'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { js[2] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.573 ns) + CELL(0.442 ns) 1.015 ns process2~26 2 COMB LC_X12_Y7_N7 2 " "Info: 2: + IC(0.573 ns) + CELL(0.442 ns) = 1.015 ns; Loc. = LC_X12_Y7_N7; Fanout = 2; COMB Node = 'process2~26'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.015 ns" { js[2] process2~26 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.477 ns) + CELL(0.292 ns) 1.784 ns js~163 3 COMB LC_X12_Y7_N6 3 " "Info: 3: + IC(0.477 ns) + CELL(0.292 ns) = 1.784 ns; Loc. = LC_X12_Y7_N6; Fanout = 3; COMB Node = 'js~163'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "0.769 ns" { process2~26 js~163 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.738 ns) 2.978 ns js\[3\] 4 REG LC_X12_Y7_N4 4 " "Info: 4: + IC(0.456 ns) + CELL(0.738 ns) = 2.978 ns; Loc. = LC_X12_Y7_N4; Fanout = 4; REG Node = 'js\[3\]'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.194 ns" { js~163 js[3] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns 49.43 % " "Info: Total cell delay = 1.472 ns ( 49.43 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.506 ns 50.57 % " "Info: Total interconnect delay = 1.506 ns ( 50.57 % )" { } { } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.978 ns" { js[2] process2~26 js~163 js[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.978 ns" { js[2] process2~26 js~163 js[3] } { 0.000ns 0.573ns 0.477ns 0.456ns } { 0.000ns 0.442ns 0.292ns 0.738ns } } } } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[3] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[2] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.978 ns" { js[2] process2~26 js~163 js[3] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.978 ns" { js[2] process2~26 js~163 js[3] } { 0.000ns 0.573ns 0.477ns 0.456ns } { 0.000ns 0.442ns 0.292ns 0.738ns } } } } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clkx8 register merrval_high\[1\] register width\[1\]~reg0 1.054 ns " "Info: Minimum slack time is 1.054 ns for clock \"clkx8\" between source register \"merrval_high\[1\]\" and destination register \"width\[1\]~reg0\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.845 ns + Shortest register register " "Info: + Shortest register to register delay is 0.845 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns merrval_high\[1\] 1 REG LC_X13_Y12_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y12_N3; Fanout = 1; REG Node = 'merrval_high\[1\]'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { merrval_high[1] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.309 ns) 0.845 ns width\[1\]~reg0 2 REG LC_X13_Y12_N4 1 " "Info: 2: + IC(0.536 ns) + CELL(0.309 ns) = 0.845 ns; Loc. = LC_X13_Y12_N4; Fanout = 1; REG Node = 'width\[1\]~reg0'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "0.845 ns" { merrval_high[1] width[1]~reg0 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 205 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 36.57 % " "Info: Total cell delay = 0.309 ns ( 36.57 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.536 ns 63.43 % " "Info: Total interconnect delay = 0.536 ns ( 63.43 % )" { } { } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "0.845 ns" { merrval_high[1] width[1]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "0.845 ns" { merrval_high[1] width[1]~reg0 } { 0.0ns 0.536ns } { 0.0ns 0.309ns } } } } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clkx8 10.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clkx8\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clkx8 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clkx8\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx8 destination 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clkx8\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx8 1 CLK PIN_29 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 50; CLK Node = 'clkx8'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { clkx8 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns width\[1\]~reg0 2 REG LC_X13_Y12_N4 1 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y12_N4; Fanout = 1; REG Node = 'width\[1\]~reg0'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.456 ns" { clkx8 width[1]~reg0 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 205 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" { } { } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 width[1]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 width[1]~reg0 } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx8 source 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"clkx8\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx8 1 CLK PIN_29 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 50; CLK Node = 'clkx8'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { clkx8 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns merrval_high\[1\] 2 REG LC_X13_Y12_N3 1 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y12_N3; Fanout = 1; REG Node = 'merrval_high\[1\]'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.456 ns" { clkx8 merrval_high[1] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" { } { } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 merrval_high[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 merrval_high[1] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 width[1]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 width[1]~reg0 } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 merrval_high[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 merrval_high[1] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 205 -1 0 } } } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 width[1]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 width[1]~reg0 } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 merrval_high[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 merrval_high[1] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "0.845 ns" { merrval_high[1] width[1]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "0.845 ns" { merrval_high[1] width[1]~reg0 } { 0.0ns 0.536ns } { 0.0ns 0.309ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 width[1]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 width[1]~reg0 } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 merrval_high[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 merrval_high[1] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clkx10 register js\[0\] register js\[2\] 1.156 ns " "Info: Minimum slack time is 1.156 ns for clock \"clkx10\" between source register \"js\[0\]\" and destination register \"js\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.947 ns + Shortest register register " "Info: + Shortest register to register delay is 0.947 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns js\[0\] 1 REG LC_X12_Y7_N0 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y7_N0; Fanout = 6; REG Node = 'js\[0\]'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { js[0] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.309 ns) 0.947 ns js\[2\] 2 REG LC_X12_Y7_N5 4 " "Info: 2: + IC(0.638 ns) + CELL(0.309 ns) = 0.947 ns; Loc. = LC_X12_Y7_N5; Fanout = 4; REG Node = 'js\[2\]'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "0.947 ns" { js[0] js[2] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 32.63 % " "Info: Total cell delay = 0.309 ns ( 32.63 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.638 ns 67.37 % " "Info: Total interconnect delay = 0.638 ns ( 67.37 % )" { } { } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "0.947 ns" { js[0] js[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "0.947 ns" { js[0] js[2] } { 0.0ns 0.638ns } { 0.0ns 0.309ns } } } } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clkx10 10.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clkx10\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clkx10 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clkx10\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx10 destination 2.903 ns + Longest register " "Info: + Longest clock path from clock \"clkx10\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx10 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clkx10'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { clkx10 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns js\[2\] 2 REG LC_X12_Y7_N5 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X12_Y7_N5; Fanout = 4; REG Node = 'js\[2\]'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.434 ns" { clkx10 js[2] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" { } { } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[2] } { 0.0ns 0.0ns 0.723ns } { 0.0ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx10 source 2.903 ns - Shortest register " "Info: - Shortest clock path from clock \"clkx10\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx10 1 CLK PIN_28 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 33; CLK Node = 'clkx10'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { clkx10 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns js\[0\] 2 REG LC_X12_Y7_N0 6 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X12_Y7_N0; Fanout = 6; REG Node = 'js\[0\]'" { } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.434 ns" { clkx10 js[0] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" { } { } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[0] } { 0.0ns 0.0ns 0.723ns } { 0.0ns 1.469ns 0.711ns } } } } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[2] } { 0.0ns 0.0ns 0.723ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[0] } { 0.0ns 0.0ns 0.723ns } { 0.0ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 48 -1 0 } } } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[2] } { 0.0ns 0.0ns 0.723ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[0] } { 0.0ns 0.0ns 0.723ns } { 0.0ns 1.469ns 0.711ns } } } } 0} } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "0.947 ns" { js[0] js[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "0.947 ns" { js[0] js[2] } { 0.0ns 0.638ns } { 0.0ns 0.309ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[2] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[2] } { 0.0ns 0.0ns 0.723ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.903 ns" { clkx10 js[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clkx10 clkx10~out0 js[0] } { 0.0ns 0.0ns 0.723ns } { 0.0ns 1.469ns 0.711ns } } } } 0}
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