golomb2.tan.qmsg

golomb编码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkx8 " "Info: Assuming node \"clkx8\" is an undefined clock" {  } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkx8" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clkx10 " "Info: Assuming node \"clkx10\" is an undefined clock" {  } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } } { "d:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkx10" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clkx8 register count\[1\] register width\[2\]~reg0 3.97 ns " "Info: Slack time is 3.97 ns for clock \"clkx8\" between source register \"count\[1\]\" and destination register \"width\[2\]~reg0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "165.84 MHz 6.03 ns " "Info: Fmax is 165.84 MHz (period= 6.03 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.739 ns + Largest register register " "Info: + Largest register to register requirement is 9.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clkx8 10.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clkx8\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clkx8 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clkx8\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx8 destination 2.925 ns + Shortest register " "Info: + Shortest clock path from clock \"clkx8\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx8 1 CLK PIN_29 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 50; CLK Node = 'clkx8'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { clkx8 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns width\[2\]~reg0 2 REG LC_X13_Y12_N7 1 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y12_N7; Fanout = 1; REG Node = 'width\[2\]~reg0'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.456 ns" { clkx8 width[2]~reg0 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 205 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 width[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 width[2]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx8 source 2.925 ns - Longest register " "Info: - Longest clock path from clock \"clkx8\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkx8 1 CLK PIN_29 50 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 50; CLK Node = 'clkx8'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { clkx8 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns count\[1\] 2 REG LC_X14_Y12_N8 17 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y12_N8; Fanout = 17; REG Node = 'count\[1\]'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.456 ns" { clkx8 count[1] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 count[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 count[1] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 width[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 width[2]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 count[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 count[1] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 205 -1 0 } }  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 width[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 width[2]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 count[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 count[1] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.769 ns - Longest register register " "Info: - Longest register to register delay is 5.769 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC_X14_Y12_N8 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y12_N8; Fanout = 17; REG Node = 'count\[1\]'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "" { count[1] } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.366 ns) + CELL(0.590 ns) 1.956 ns width~1007 2 COMB LC_X13_Y10_N9 4 " "Info: 2: + IC(1.366 ns) + CELL(0.590 ns) = 1.956 ns; Loc. = LC_X13_Y10_N9; Fanout = 4; COMB Node = 'width~1007'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.956 ns" { count[1] width~1007 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.534 ns) + CELL(0.590 ns) 4.080 ns width~1011 3 COMB LC_X12_Y12_N1 1 " "Info: 3: + IC(1.534 ns) + CELL(0.590 ns) = 4.080 ns; Loc. = LC_X12_Y12_N1; Fanout = 1; COMB Node = 'width~1011'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.124 ns" { width~1007 width~1011 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.082 ns) + CELL(0.607 ns) 5.769 ns width\[2\]~reg0 4 REG LC_X13_Y12_N7 1 " "Info: 4: + IC(1.082 ns) + CELL(0.607 ns) = 5.769 ns; Loc. = LC_X13_Y12_N7; Fanout = 1; REG Node = 'width\[2\]~reg0'" {  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "1.689 ns" { width~1011 width[2]~reg0 } "NODE_NAME" } "" } } { "golomb2.vhd" "" { Text "E:/work/VHDL/jpeg-ls/golomb2/golomb2.vhd" 205 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.787 ns 30.98 % " "Info: Total cell delay = 1.787 ns ( 30.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.982 ns 69.02 % " "Info: Total interconnect delay = 3.982 ns ( 69.02 % )" {  } {  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "5.769 ns" { count[1] width~1007 width~1011 width[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.769 ns" { count[1] width~1007 width~1011 width[2]~reg0 } { 0.000ns 1.366ns 1.534ns 1.082ns } { 0.000ns 0.590ns 0.590ns 0.607ns } } }  } 0}  } { { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 width[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 width[2]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "2.925 ns" { clkx8 count[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clkx8 clkx8~out0 count[1] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" "" { Report "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2_cmp.qrpt" Compiler "golomb2" "UNKNOWN" "V1" "E:/work/VHDL/jpeg-ls/golomb2/db/golomb2.quartus_db" { Floorplan "E:/work/VHDL/jpeg-ls/golomb2/" "" "5.769 ns" { count[1] width~1007 width~1011 width[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "5.769 ns" { count[1] width~1007 width~1011 width[2]~reg0 } { 0.000ns 1.366ns 1.534ns 1.082ns } { 0.000ns 0.590ns 0.590ns 0.607ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0}