golomb2.tan.rpt

golomb编码

Timing Analyzer report for golomb2
Wed May 10 15:55:55 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clkx8'
  6. Clock Setup: 'clkx10'
  7. Clock Hold: 'clkx8'
  8. Clock Hold: 'clkx10'
  9. tsu
 10. tco
 11. th
 12. Minimum tco
 13. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                ;
+------------------------------+----------+-----------------------------------+------------------------------------------------+------------------+---------------+------------+----------+--------------+
; Type                         ; Slack    ; Required Time                     ; Actual Time                                    ; From             ; To            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+----------+-----------------------------------+------------------------------------------------+------------------+---------------+------------+----------+--------------+
; Worst-case tsu               ; N/A      ; None                              ; 5.780 ns                                       ; wen              ; err[5]        ;            ; clkx10   ; 0            ;
; Worst-case tco               ; N/A      ; None                              ; 8.213 ns                                       ; dataout[21]~reg0 ; dataout[21]   ; clkx8      ;          ; 0            ;
; Worst-case th                ; N/A      ; None                              ; -4.198 ns                                      ; Nq[7]            ; nq1[7]        ;            ; clkx10   ; 0            ;
; Worst-case Minimum tco       ; N/A      ; None                              ; 7.406 ns                                       ; width[1]~reg0    ; width[1]      ; clkx8      ;          ; 0            ;
; Clock Setup: 'clkx8'         ; 3.970 ns ; 100.00 MHz ( period = 10.000 ns ) ; 165.84 MHz ( period = 6.030 ns )               ; count[1]         ; width[2]~reg0 ; clkx8      ; clkx8    ; 0            ;
; Clock Setup: 'clkx10'        ; 6.761 ns ; 100.00 MHz ( period = 10.000 ns ) ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; js[2]            ; js[3]         ; clkx10     ; clkx10   ; 0            ;
; Clock Hold: 'clkx8'          ; 1.054 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A                                            ; merrval_high[1]  ; width[1]~reg0 ; clkx8      ; clkx8    ; 0            ;
; Clock Hold: 'clkx10'         ; 1.156 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A                                            ; js[0]            ; js[2]         ; clkx10     ; clkx10   ; 0            ;
; Total number of failed paths ;          ;                                   ;                                                ;                  ;               ;            ;          ; 0            ;
+------------------------------+----------+-----------------------------------+------------------------------------------------+------------------+---------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;