rei2c.map.qmsg

用VHDL编写的quartusii平台上的串行EEPROM配置读取的程序。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 24 14:39:40 2006 " "Info: Processing started: Mon Jul 24 14:39:40 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off rei2c -c rei2c " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rei2c -c rei2c" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rei2c.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rei2c.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rei2c-RTL " "Info: Found design unit 1: rei2c-RTL" {  } { { "rei2c.vhd" "" { Text "E:/Work/camera/software/eeprom/rei2c/rei2c.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rei2c " "Info: Found entity 1: rei2c" {  } { { "rei2c.vhd" "" { Text "E:/Work/camera/software/eeprom/rei2c/rei2c.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "rei2c " "Info: Elaborating entity \"rei2c\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|rei2c\|state 11 0 " "Info: State machine \"\|rei2c\|state\" contains 11 states and 0 state bits" {  } { { "rei2c.vhd" "" { Text "E:/Work/camera/software/eeprom/rei2c/rei2c.vhd" 30 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|rei2c\|state " "Info: Selected Auto state machine encoding method for state machine \"\|rei2c\|state\"" {  } { { "rei2c.vhd" "" { Text "E:/Work/camera/software/eeprom/rei2c/rei2c.vhd" 30 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|rei2c\|state " "Info: Encoding result for state machine \"\|rei2c\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "11 " "Info: Completed encoding using 11 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.quit " "Info: Encoded state bit \"state.quit\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.stop " "Info: Encoded state bit \"state.stop\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.transfer " "Info: Encoded state bit \"state.transfer\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.control2 " "Info: Encoded state bit \"state.control2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.start2 " "Info: Encoded state bit \"state.start2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.initial2 " "Info: Encoded state bit \"state.initial2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.lowadd " "Info: Encoded state bit \"state.lowadd\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.highadd " "Info: Encoded state bit \"state.highadd\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.control1 " "Info: Encoded state bit \"state.control1\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.start1 " "Info: Encoded state bit \"state.start1\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.initial1 " "Info: Encoded state bit \"state.initial1\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.initial1 00000000000 " "Info: State \"\|rei2c\|state.initial1\" uses code string \"00000000000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.start1 00000000011 " "Info: State \"\|rei2c\|state.start1\" uses code string \"00000000011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.control1 00000000101 " "Info: State \"\|rei2c\|state.control1\" uses code string \"00000000101\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.highadd 00000001001 " "Info: State \"\|rei2c\|state.highadd\" uses code string \"00000001001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.lowadd 00000010001 " "Info: State \"\|rei2c\|state.lowadd\" uses code string \"00000010001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.initial2 00000100001 " "Info: State \"\|rei2c\|state.initial2\" uses code string \"00000100001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.start2 00001000001 " "Info: State \"\|rei2c\|state.start2\" uses code string \"00001000001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.control2 00010000001 " "Info: State \"\|rei2c\|state.control2\" uses code string \"00010000001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.transfer 00100000001 " "Info: State \"\|rei2c\|state.transfer\" uses code string \"00100000001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.stop 01000000001 " "Info: State \"\|rei2c\|state.stop\" uses code string \"01000000001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|rei2c\|state.quit 10000000001 " "Info: State \"\|rei2c\|state.quit\" uses code string \"10000000001\"" {  } {  } 0}  } { { "rei2c.vhd" "" { Text "E:/Work/camera/software/eeprom/rei2c/rei2c.vhd" 30 -1 0 } }  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "rei2c.vhd" "" { Text "E:/Work/camera/software/eeprom/rei2c/rei2c.vhd" 13 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "112 " "Info: Implemented 112 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "98 " "Info: Implemented 98 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 24 14:39:45 2006 " "Info: Processing ended: Mon Jul 24 14:39:45 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}