fir_st.v

Quartus中实现的DDS 使用的是altera提供的IP core

defparam Ur3_n_3_pp.C2 =                  112;
defparam Ur3_n_3_pp.C3 =                  211;
defparam Ur3_n_3_pp.C4 =                  122;
defparam Ur3_n_3_pp.C5 =                  221;
defparam Ur3_n_3_pp.C6 =                  234;
defparam Ur3_n_3_pp.C7 =                  333;
defparam Ur3_n_3_pp.C8 =                  127;
defparam Ur3_n_3_pp.C9 =                  226;
defparam Ur3_n_3_pp.CA =                  239;
defparam Ur3_n_3_pp.CB =                  338;
defparam Ur3_n_3_pp.CC =                  249;
defparam Ur3_n_3_pp.CD =                  348;
defparam Ur3_n_3_pp.CE =                  361;
defparam Ur3_n_3_pp.CF =                  460;
wire [9:0] lut_val_3_n_4_pp;
rom_lut_r_cen Ur3_n_4_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[4],sym_res_14_n[4],sym_res_13_n[4],sym_res_12_n[4] } ), .data_out( lut_val_3_n_4_pp[9:0]) ) ;
 defparam Ur3_n_4_pp.DATA_WIDTH = 10;
defparam Ur3_n_4_pp.C0 =                    0;
defparam Ur3_n_4_pp.C1 =                   99;
defparam Ur3_n_4_pp.C2 =                  112;
defparam Ur3_n_4_pp.C3 =                  211;
defparam Ur3_n_4_pp.C4 =                  122;
defparam Ur3_n_4_pp.C5 =                  221;
defparam Ur3_n_4_pp.C6 =                  234;
defparam Ur3_n_4_pp.C7 =                  333;
defparam Ur3_n_4_pp.C8 =                  127;
defparam Ur3_n_4_pp.C9 =                  226;
defparam Ur3_n_4_pp.CA =                  239;
defparam Ur3_n_4_pp.CB =                  338;
defparam Ur3_n_4_pp.CC =                  249;
defparam Ur3_n_4_pp.CD =                  348;
defparam Ur3_n_4_pp.CE =                  361;
defparam Ur3_n_4_pp.CF =                  460;
wire [9:0] lut_val_3_n_5_pp;
rom_lut_r_cen Ur3_n_5_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[5],sym_res_14_n[5],sym_res_13_n[5],sym_res_12_n[5] } ), .data_out( lut_val_3_n_5_pp[9:0]) ) ;
 defparam Ur3_n_5_pp.DATA_WIDTH = 10;
defparam Ur3_n_5_pp.C0 =                    0;
defparam Ur3_n_5_pp.C1 =                   99;
defparam Ur3_n_5_pp.C2 =                  112;
defparam Ur3_n_5_pp.C3 =                  211;
defparam Ur3_n_5_pp.C4 =                  122;
defparam Ur3_n_5_pp.C5 =                  221;
defparam Ur3_n_5_pp.C6 =                  234;
defparam Ur3_n_5_pp.C7 =                  333;
defparam Ur3_n_5_pp.C8 =                  127;
defparam Ur3_n_5_pp.C9 =                  226;
defparam Ur3_n_5_pp.CA =                  239;
defparam Ur3_n_5_pp.CB =                  338;
defparam Ur3_n_5_pp.CC =                  249;
defparam Ur3_n_5_pp.CD =                  348;
defparam Ur3_n_5_pp.CE =                  361;
defparam Ur3_n_5_pp.CF =                  460;
wire [9:0] lut_val_3_n_6_pp;
rom_lut_r_cen Ur3_n_6_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[6],sym_res_14_n[6],sym_res_13_n[6],sym_res_12_n[6] } ), .data_out( lut_val_3_n_6_pp[9:0]) ) ;
 defparam Ur3_n_6_pp.DATA_WIDTH = 10;
defparam Ur3_n_6_pp.C0 =                    0;
defparam Ur3_n_6_pp.C1 =                   99;
defparam Ur3_n_6_pp.C2 =                  112;
defparam Ur3_n_6_pp.C3 =                  211;
defparam Ur3_n_6_pp.C4 =                  122;
defparam Ur3_n_6_pp.C5 =                  221;
defparam Ur3_n_6_pp.C6 =                  234;
defparam Ur3_n_6_pp.C7 =                  333;
defparam Ur3_n_6_pp.C8 =                  127;
defparam Ur3_n_6_pp.C9 =                  226;
defparam Ur3_n_6_pp.CA =                  239;
defparam Ur3_n_6_pp.CB =                  338;
defparam Ur3_n_6_pp.CC =                  249;
defparam Ur3_n_6_pp.CD =                  348;
defparam Ur3_n_6_pp.CE =                  361;
defparam Ur3_n_6_pp.CF =                  460;
wire [9:0] lut_val_3_n_7_pp;
rom_lut_r_cen Ur3_n_7_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[7],sym_res_14_n[7],sym_res_13_n[7],sym_res_12_n[7] } ), .data_out( lut_val_3_n_7_pp[9:0]) ) ;
 defparam Ur3_n_7_pp.DATA_WIDTH = 10;
defparam Ur3_n_7_pp.C0 =                    0;
defparam Ur3_n_7_pp.C1 =                   99;
defparam Ur3_n_7_pp.C2 =                  112;
defparam Ur3_n_7_pp.C3 =                  211;
defparam Ur3_n_7_pp.C4 =                  122;
defparam Ur3_n_7_pp.C5 =                  221;
defparam Ur3_n_7_pp.C6 =                  234;
defparam Ur3_n_7_pp.C7 =                  333;
defparam Ur3_n_7_pp.C8 =                  127;
defparam Ur3_n_7_pp.C9 =                  226;
defparam Ur3_n_7_pp.CA =                  239;
defparam Ur3_n_7_pp.CB =                  338;
defparam Ur3_n_7_pp.CC =                  249;
defparam Ur3_n_7_pp.CD =                  348;
defparam Ur3_n_7_pp.CE =                  361;
defparam Ur3_n_7_pp.CF =                  460;
wire [9:0] lut_val_3_n_8_pp;
rom_lut_r_cen Ur3_n_8_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[8],sym_res_14_n[8],sym_res_13_n[8],sym_res_12_n[8] } ), .data_out( lut_val_3_n_8_pp[9:0]) ) ;
 defparam Ur3_n_8_pp.DATA_WIDTH = 10;
defparam Ur3_n_8_pp.C0 =                    0;
defparam Ur3_n_8_pp.C1 =                   99;
defparam Ur3_n_8_pp.C2 =                  112;
defparam Ur3_n_8_pp.C3 =                  211;
defparam Ur3_n_8_pp.C4 =                  122;
defparam Ur3_n_8_pp.C5 =                  221;
defparam Ur3_n_8_pp.C6 =                  234;
defparam Ur3_n_8_pp.C7 =                  333;
defparam Ur3_n_8_pp.C8 =                  127;
defparam Ur3_n_8_pp.C9 =                  226;
defparam Ur3_n_8_pp.CA =                  239;
defparam Ur3_n_8_pp.CB =                  338;
defparam Ur3_n_8_pp.CC =                  249;
defparam Ur3_n_8_pp.CD =                  348;
defparam Ur3_n_8_pp.CE =                  361;
defparam Ur3_n_8_pp.CF =                  460;
wire [9:0] lut_val_3_n_9_pp;
rom_lut_r_cen Ur3_n_9_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[9],sym_res_14_n[9],sym_res_13_n[9],sym_res_12_n[9] } ), .data_out( lut_val_3_n_9_pp[9:0]) ) ;
 defparam Ur3_n_9_pp.DATA_WIDTH = 10;
defparam Ur3_n_9_pp.C0 =                    0;
defparam Ur3_n_9_pp.C1 =                   99;
defparam Ur3_n_9_pp.C2 =                  112;
defparam Ur3_n_9_pp.C3 =                  211;
defparam Ur3_n_9_pp.C4 =                  122;
defparam Ur3_n_9_pp.C5 =                  221;
defparam Ur3_n_9_pp.C6 =                  234;
defparam Ur3_n_9_pp.C7 =                  333;
defparam Ur3_n_9_pp.C8 =                  127;
defparam Ur3_n_9_pp.C9 =                  226;
defparam Ur3_n_9_pp.CA =                  239;
defparam Ur3_n_9_pp.CB =                  338;
defparam Ur3_n_9_pp.CC =                  249;
defparam Ur3_n_9_pp.CD =                  348;
defparam Ur3_n_9_pp.CE =                  361;
defparam Ur3_n_9_pp.CF =                  460;
wire [9:0] lut_val_3_n_10_pp;
rom_lut_r_cen Ur3_n_10_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_15_n[10],sym_res_14_n[10],sym_res_13_n[10],sym_res_12_n[10] } ), .data_out( lut_val_3_n_10_pp[9:0]) ) ;
 defparam Ur3_n_10_pp.DATA_WIDTH = 10;
defparam Ur3_n_10_pp.C0 =                    0;
defparam Ur3_n_10_pp.C1 =                  925;
defparam Ur3_n_10_pp.C2 =                  912;
defparam Ur3_n_10_pp.C3 =                  813;
defparam Ur3_n_10_pp.C4 =                  902;
defparam Ur3_n_10_pp.C5 =                  803;
defparam Ur3_n_10_pp.C6 =                  790;
defparam Ur3_n_10_pp.C7 =                  691;
defparam Ur3_n_10_pp.C8 =                  897;
defparam Ur3_n_10_pp.C9 =                  798;
defparam Ur3_n_10_pp.CA =                  785;
defparam Ur3_n_10_pp.CB =                  686;
defparam Ur3_n_10_pp.CC =                  775;
defparam Ur3_n_10_pp.CD =                  676;
defparam Ur3_n_10_pp.CE =                  663;
defparam Ur3_n_10_pp.CF =                  564;


// ---- partial product adder tree ----

wire [19:0] lut_0_bit_0_fill;
wire [19:0] lut_0_bit_1_fill;
wire [19:0] lut_0_bit_2_fill;
wire [19:0] lut_0_bit_3_fill;
wire [19:0] lut_0_bit_4_fill;
wire [19:0] lut_0_bit_5_fill;
wire [19:0] lut_0_bit_6_fill;
wire [19:0] lut_0_bit_7_fill;
wire [19:0] lut_0_bit_8_fill;
wire [19:0] lut_0_bit_9_fill;
wire [19:0] lut_0_bit_10_fill;
assign lut_0_bit_0_fill = {lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9], lut_val_0_n_0_pp[9],  lut_val_0_n_0_pp };
assign lut_0_bit_1_fill = {lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9], lut_val_0_n_1_pp[9],  lut_val_0_n_1_pp, 1'd0 };
assign lut_0_bit_2_fill = {lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9], lut_val_0_n_2_pp[9],  lut_val_0_n_2_pp, 2'd0 };
assign lut_0_bit_3_fill = {lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9], lut_val_0_n_3_pp[9],  lut_val_0_n_3_pp, 3'd0 };
assign lut_0_bit_4_fill = {lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9], lut_val_0_n_4_pp[9],  lut_val_0_n_4_pp, 4'd0 };
assign lut_0_bit_5_fill = {lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9], lut_val_0_n_5_pp[9],  lut_val_0_n_5_pp, 5'd0 };
assign lut_0_bit_6_fill = {lut_val_0_n_6_pp[9], lut_val_0_n_6_pp[9], lut_val_0_n_6_pp[9], lut_val_0_n_6_pp[9],  lut_val_0_n_6_pp, 6'd0 };
assign lut_0_bit_7_fill = {lut_val_0_n_7_pp[9], lut_val_0_n_7_pp[9], lut_val_0_n_7_pp[9],  lut_val_0_n_7_pp, 7'd0 };
assign lut_0_bit_8_fill = {lut_val_0_n_8_pp[9], lut_val_0_n_8_pp[9],  lut_val_0_n_8_pp, 8'd0 };
assign lut_0_bit_9_fill = {lut_val_0_n_9_pp[9],  lut_val_0_n_9_pp, 9'd0 };
assign lut_0_bit_10_fill = { lut_val_0_n_10_pp, 10'd0 };
wire [20:0] tree_0_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_0_fill), .bin(lut_0_bit_1_fill), .res(tree_0_pp_l_0_n_0_n) );
defparam Uadd_0_lut_l_0_n_0_n.IN_WIDTH = 20;
defparam Uadd_0_lut_l_0_n_0_n.PIPE_DEPTH = 1;
wire [20:0] tree_0_pp_l_0_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_2_fill), .bin(lut_0_bit_3_fill), .res(tree_0_pp_l_0_n_1_n) );
defparam Uadd_0_lut_l_0_n_1_n.IN_WIDTH = 20;
defparam Uadd_0_lut_l_0_n_1_n.PIPE_DEPTH = 1;
wire [20:0] tree_0_pp_l_0_n_2_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_2_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_4_fill), .bin(lut_0_bit_5_fill), .res(tree_0_pp_l_0_n_2_n) );
defparam Uadd_0_lut_l_0_n_2_n.IN_WIDTH = 20;
defparam Uadd_0_lut_l_0_n_2_n.PIPE_DEPTH = 1;
wire [20:0] tree_0_pp_l_0_n_3_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_3_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_6_fill), .bin(lut_0_bit_7_fill), .res(tree_0_pp_l_0_n_3_n) );
defparam Uadd_0_lut_l_0_n_3_n.IN_WIDTH = 20;
defparam Uadd_0_lut_l_0_n_3_n.PIPE_DEPTH = 1;
wire [20:0] tree_0_pp_l_0_n_4_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_4_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_8_fill), .bin(lut_0_bit_9_fill), .res(tree_0_pp_l_0_n_4_n) );
defparam Uadd_0_lut_l_0_n_4_n.IN_WIDTH = 20;
defparam Uadd_0_lut_l_0_n_4_n.PIPE_DEPTH = 1;
wire [20:0] tree_0_pp_l_0_n_5_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_5_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_10_fill), .bin(20'd0), .res(tree_0_pp_l_0_n_5_n) );
defparam Uadd_0_lut_l_0_n_5_n.IN_WIDTH = 20;
defparam Uadd_0_lut_l_0_n_5_n.PIPE_DEPTH = 1;

wire [21:0] tree_0_pp_l_1_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_0_n), .bin(tree_0_pp_l_0_n_1_n), .res(tree_0_pp_l_1_n_0_n) );
defparam Uadd_0_lut_l_1_n_0_n.IN_WIDTH = 21;
defparam Uadd_0_lut_l_1_n_0_n.PIPE_DEPTH = 1;
wire [21:0] tree_0_pp_l_1_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_2_n), .bin(tree_0_pp_l_0_n_3_n), .res(tree_0_pp_l_1_n_1_n) );
defparam Uadd_0_lut_l_1_n_1_n.IN_WIDTH = 21;
defparam Uadd_0_lut_l_1_n_1_n.PIPE_DEPTH = 1;
wire [21:0] tree_0_pp_l_1_n_2_n;
sadd_lpm_cen Uadd_0_lut_l_1_n_2_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_0_n_4_n), .bin(tree_0_pp_l_0_n_5_n), .res(tree_0_pp_l_1_n_2_n) );
defparam Uadd_0_lut_l_1_n_2_n.IN_WIDTH = 21;
defparam Uadd_0_lut_l_1_n_2_n.PIPE_DEPTH = 1;

wire [22:0] tree_0_pp_l_2_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_2_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_1_n_0_n), .bin(tree_0_pp_l_1_n_1_n), .res(tree_0_pp_l_2_n_0_n) );
defparam Uadd_0_lut_l_2_n_0_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_2_n_0_n.PIPE_DEPTH = 1;
wire [22:0] tree_0_pp_l_2_n_1_n;
sadd_lpm_cen Uadd_0_lut_l_2_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_1_n_2_n), .bin(22'd0), .res(tree_0_pp_l_2_n_1_n) );
defparam Uadd_0_lut_l_2_n_1_n.IN_WIDTH = 22;
defparam Uadd_0_lut_l_2_n_1_n.PIPE_DEPTH = 1;

wire [23:0] tree_0_pp_l_3_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_3_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(tree_0_pp_l_2_n_0_n), .bin(tree_0_pp_l_2_n_1_n), .res(tree_0_pp_l_3_n_0_n) );
defparam Uadd_0_lut_l_3_n_0_n.IN_WIDTH = 23;
defparam Uadd_0_lut_l_3_n_0_n.PIPE_DEPTH = 1;

wire [23:0] lut_val_0_n;
assign lut_val_0_n=tree_0_pp_l_3_n_0_n;


// ---- partial product adder tree ----

wire [19:0] lut_1_bit_0_fill;
wire [19:0] lut_1_bit_1_fill;
wire [19:0] lut_1_bit_2_fill;
wire [19:0] lut_1_bit_3_fill;
wire [19:0] lut_1_bit_4_fill;
wire [19:0] lut_1_bit_5_fill;
wire [19:0] lut_1_bit_6_fill;
wire [19:0] lut_1_bit_7_fill;
wire [19:0] lut_1_bit_8_fill;
wire [19:0] lut_1_bit_9_fill;
wire [19:0] lut_1_bit_10_fill;
assign lut_1_bit_0_fill = {lut_val_1_n_0_pp[9], lut_val_1_n_0_pp[9], lut_val_1_n_0_pp[9], lut_val_1_n_0_pp[9], lut_val_1_n_0_pp[9], lut_val_1_n_0_pp[9], lut_val_1_n_0_pp[9], lut_val_1_n_0_pp[9], lut_val_1_n_0_pp[9], lut_val_1_n_0_pp[9],  lut_val_1_n_0_pp };
assign lut_1_bit_1_fill = {lut_val_1_n_1_pp[9], lut_val_1_n_1_pp[9], lut_val_1_n_1_pp[9]