fir_nativelink.tcl

Quartus中实现的DDS 使用的是altera提供的IP core

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catch {set testbench_files [glob -nocomplain *.hex]} error_msg
puts "$error_msg"
  
catch {set coef_files [glob -nocomplain FIR_coef*.txt]} error_msg
puts "$error_msg"
  
# The top-level in HDL type "VERILOG"
set ipfs_ext vo
if {[file exists FIR.vo]} {
	set hdl_ext v
} else {
	puts "Warning: Could not find FIR.$ipfs_ext!"
}

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation

# Set test bench name
set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation


# test bench settings
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME DUT -section_id tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME work.tb_FIR -section_id tb
set_global_assignment -name EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY work -section_id tb

# IPFS file
set_global_assignment -name EDA_IPFS_FILE FIR.$ipfs_ext -section_id eda_simulation -library work

# Add Testbench files
foreach i $testbench_files {
  set_global_assignment -name EDA_TEST_BENCH_FILE $i -section_id tb -library work
}
# Add coef files
foreach i $coef_files {
  set_global_assignment -name EDA_TEST_BENCH_FILE $i -section_id tb -library work
}
set_global_assignment -name EDA_TEST_BENCH_FILE FIR_input.txt -section_id tb -library work

set_global_assignment -name EDA_TEST_BENCH_FILE tb_FIR.vhd -section_id tb -library work

# Specify testbench mode for nativelink
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation

# Specify active testbench for nativelink
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation