📄 fir.v
字号:
// megafunction wizard: %FIR Compiler v8.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// FIR_ast
// ============================================================
// Generated by FIR Compiler 8.1 [Altera, IP Toolbench 1.3.0 Build 163]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2009 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module FIR (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error);
input clk;
input reset_n;
input [9:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
output [20:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
FIR_ast FIR_ast_inst(
.clk(clk),
.reset_n(reset_n),
.ast_sink_data(ast_sink_data),
.ast_sink_valid(ast_sink_valid),
.ast_source_ready(ast_source_ready),
.ast_sink_error(ast_sink_error),
.ast_source_data(ast_source_data),
.ast_sink_ready(ast_sink_ready),
.ast_source_valid(ast_source_valid),
.ast_source_error(ast_source_error));
endmodule
// =========================================================
// FIR Compiler Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, FIR Compiler Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="FIR Compiler" version="8.1" build="163" iptb_version="1.3.0 Build 163" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.FIRModelClass" active_core="FIR_ast" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "use_mem" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "mem_type" value="M512" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filter_rate" value="Single Rate" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filter_factor" value="2" type="INTEGER" enable="0" />
// Retrieval info: <PRIVATE name = "coefficient_scaling_type" value="Auto" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "coefficient_scaling_factor" value="1167.5369231683899" type="STRING" enable="0" />
// Retrieval info: <PRIVATE name = "coefficient_bit_width" value="8" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "coefficient_binary_point_position" value="0" type="INTEGER" enable="0" />
// Retrieval info: <PRIVATE name = "number_of_input_channels" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "input_number_system" value="Signed Binary" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "input_bit_width" value="10" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "input_binary_point_position" value="0" type="INTEGER" enable="0" />
// Retrieval info: <PRIVATE name = "output_bit_width_method" value="Actual Coefficients" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "output_number_system" value="Full Resolution" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "output_bit_width" value="21" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "output_bits_right_of_binary_point" value="16" type="INTEGER" enable="0" />
// Retrieval info: <PRIVATE name = "output_bits_removed_from_lsb" value="0" type="INTEGER" enable="0" />
// Retrieval info: <PRIVATE name = "output_lsb_remove_type" value="Truncate" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "output_msb_remove_type" value="Truncate" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "flow_control" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "flow_control_input" value="Slave Sink" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "flow_control_output" value="Master Source" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "device_family" value="Cyclone II" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "structure" value="Distributed Arithmetic : Fully Parallel Filter" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pipeline_level" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "clocks_to_compute" value="1" type="INTEGER" enable="0" />
// Retrieval info: <PRIVATE name = "number_of_serial_units" value="2" type="INTEGER" enable="0" />
// Retrieval info: <PRIVATE name = "data_storage" value="Logic Cells" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "coefficient_storage" value="Logic Cells" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "multiplier_storage" value="Logic Cells" type="STRING" enable="0" />
// Retrieval info: <PRIVATE name = "force_non_symmetric_structure" value="0" type="BOOLEAN" enable="0" />
// Retrieval info: <PRIVATE name = "coefficients_reload" value="0" type="BOOLEAN" enable="0" />
// Retrieval info: <PRIVATE name = "coefficients_reload_sgl_clock" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "max_clocks_to_compute" value="4" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "set_1" value="Low Pass Set, Floating, Low Pass, Rectangular, 32, 1.0E7, 550000.0, 3750000.0, 0, -0.0167773, -0.0211416, -0.0234977, -0.0232638, -0.0200326, -0.0136207, -0.00409837, 0.00820039, 0.0226927, 0.0385833, 0.0549215, 0.0706734, 0.0848031, 0.096356, 0.104537, 0.108776, 0.108776, 0.104537, 0.096356, 0.0848031, 0.0706734, 0.0549215, 0.0385833, 0.0226927, 0.00820039, -0.00409837, -0.0136207, -0.0200326, -0.0232638, -0.0234977, -0.0211416, -0.0167773" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "number_of_sets" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "output_full_bit_width" value="21" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "output_full_bits_right_of_binary_point" value="16" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "coefficient_reload_bit_width" value="11" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "logic_cell" value="1273" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "m512" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "m4k" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "m144k" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "m9k" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "mlab" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "megaram" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "dsp_block" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "input_clock_period" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "output_clock_period" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "throughput" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "memory_units" value="0" type="INTEGER" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "matlab_enable" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "testbench_enable" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "testbench_simulation_clock_period" value="10.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "filename" value="FIR.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "quartus_settings">
// Retrieval info: <PRIVATE name = "DEVICE" value="EP2C5F256C6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "FAMILY" value="Cyclone II" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -