nco_tb.v

Quartus中实现的DDS 使用的是altera提供的IP core

//	Copyright (C) 1988-2007 Altera Corporation

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//	support information, device programming or simulation file, and any other
//	associated documentation or information provided by Altera or a partner
//	under Altera's Megafunction Partnership Program may be used only to
//	program PLD devices (but not masked PLD devices) from Altera.  Any other
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//	any other related documentation or information provided by Altera or a
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//   NCO ver 8.1 VERILOG HDL TESTBENCH
`timescale 1ps / 1ps
module NCO_tb;
wire [9:0] sin_val;
reg [31:0] phi;
reg [15:0] fmod;
reg [9:0] pmod;
wire out_valid;
reg reset_n;
wire reset; 
assign reset = !reset_n;
reg clken;
reg clk;

initial
  begin
    $dumpvars;
    #0 clk = 1'b0;
    #0 reset_n = 1'b0;
    #0 clken = 1'b1;
    #0 phi = 32'b00000010100011110101110000101001;
    #0 fmod = 16'b0001000000000000;
    #0 pmod = 64;
    #69999 reset_n = 1'b1;
  end

always
  begin
    #5000 clk = 1;
    #5000 clk = 0;
  end

integer sin_ch, sin_print;
initial
  begin
    sin_ch = $fopen ("fsin_o_ver_NCO.txt");
  end

always @(posedge clk)
  begin
    if(reset_n==1'b1 & out_valid==1'b1)
      begin
        if (sin_val[9:0] < (1<<9))
          sin_print = sin_val[9:0];
        else
          sin_print =  sin_val[9:0] - (1<<10);

    $fdisplay (sin_ch, "%d", sin_print);
      end
end

NCO i_NCO (
    .out_valid(out_valid),
    .fsin_o(sin_val[9:0]),
    .phi_inc_i(phi[31:0]),
    .freq_mod_i(fmod),
    .phase_mod_i(pmod),
    .reset_n(reset_n),
    .clken(clken),
    .clk(clk)
    );

endmodule