hdb3decoder.vhd

这是一个HDB3的译码器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Decoder is
	port(	clk,clr,data_p,data_n:	in std_logic;
			 data_out:	out std_logic
			);
end Decoder;

architecture behavior of Decoder is
signal data_reg: std_logic_vector(4 downto 0);
signal d_n: std_logic_vector(4 downto 0);
signal d_p: std_logic_vector(4 downto 0);
signal data: std_logic:= data_p or data_n;

begin
  Decoder: process(clk, clr)
  begin 
    data <= data_p or data_n;
    if(clr='1')  then
    data_reg <= "00000";
    d_n <= "00000";
    d_p <= "00000";
    
    elsif (clk 'event and clk= '1') then
       if(data_reg(4)='0' and data_reg(3)='0' and data_reg(2)='1'
          and data='1' and (data_n=d_n(2) or data_p=d_p(2))) then
         data_reg <= "0000" & data_reg(1);
       elsif (data_reg(4)='0' and data_reg(3)='0' and data_reg(2)='0'
          and data_reg(1)='1' and data='1' and (data_n=d_n(1) or data_p=d_p(1))) then
         data_reg <= "00001";
          else 
             data_reg <= data & data_reg(4) & data_reg(3)& data_reg(2)
                              & data_reg(1);
             d_n <= data_n & d_n(4) & d_n(3) & d_n(2) & d_n(1);
             d_p <= data_p & d_p(4) & d_p(3) & d_p(2) & d_p(1);
       end if;
     end if;
   data_out <= data_reg(0);
  end process Decoder;
end architecture behavior;