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📄 lcd_top_ba.sdf

📁 基于FPGA的LCD1602驱动
💻 SDF
📖 第 1 页 / 共 5 页
字号:
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.45:5.39:5.89) (4.53:5.50:6.00))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (12.37:15.00:16.38) (11.50:13.95:15.23))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (2.90:3.56:4.02))
     (SETUP (negedge D) (posedge CLK) (3.09:3.80:4.28))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[100\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.39:5.33:5.82) (4.47:5.42:5.92))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_7_0_a2\[84\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.33:5.25:5.74) (4.42:5.36:5.85))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "MX2")
 (INSTANCE U2\/DB8_13_0_i_m2\[2\])
 (DELAY
  (ABSOLUTE
     (PORT A (7.16:8.68:9.48) (6.91:8.38:9.15))
     (IOPATH A Y (3.58:4.40:4.97) (3.33:4.09:4.62))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.65:4.48:5.06) (3.33:4.09:4.62))
     (PORT S (13.62:16.52:18.04) (13.09:15.87:17.33))
     (IOPATH S Y (1.97:3.17:3.58) (2.00:2.62:2.96))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_First_Buf_6_0_a2\[111\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.39:5.33:5.82) (4.47:5.42:5.92))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[93\])
 (DELAY
  (ABSOLUTE
     (PORT D (9.36:11.35:12.40) (8.81:10.69:11.67))
     (PORT CLK (4.35:5.27:5.75) (4.46:5.40:5.90))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.28:5.20:5.67) (4.38:5.31:5.80))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[63\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.38:5.31:5.80) (4.48:5.44:5.94))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.37:5.30:5.79) (4.46:5.40:5.90))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_7_0_a2\[24\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.45:5.40:5.90) (4.52:5.49:5.99))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[84\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.97:2.39:2.61) (1.89:2.29:2.50))
     (PORT CLK (4.44:5.39:5.89) (4.53:5.50:6.00))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.32:5.24:5.72) (4.43:5.37:5.86))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[58\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.36:5.29:5.78) (4.45:5.40:5.89))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[34\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.42:5.37:5.86) (4.50:5.46:5.96))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (8.29:10.06:10.98) (7.93:9.62:10.50))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_First_Buf_6_0_a2\[103\])
 (DELAY
  (ABSOLUTE
     (PORT A (9.57:11.61:12.68) (8.96:10.87:11.87))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.37:5.30:5.78) (4.45:5.40:5.90))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[107\])
 (DELAY
  (ABSOLUTE
     (PORT D (6.76:8.20:8.95) (6.44:7.82:8.53))
     (PORT CLK (4.55:5.52:6.03) (4.62:5.60:6.12))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.30:5.21:5.69) (4.39:5.33:5.82))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "MX2")
 (INSTANCE U2\/DB8\[6\]\/U0)
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.06:3.76:4.24) (3.12:3.83:4.32))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.15:3.88:4.37) (3.08:3.78:4.27))
     (PORT S (7.01:8.50:9.29) (6.62:8.03:8.77))
     (IOPATH S Y (2.58:3.36:3.79) (2.52:3.44:3.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[46\])
 (DELAY
  (ABSOLUTE
     (PORT D (6.76:8.19:8.95) (6.43:7.80:8.52))
     (PORT CLK (4.35:5.27:5.75) (4.46:5.41:5.90))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.33:5.26:5.74) (4.42:5.36:5.85))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[96\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.40:5.33:5.82) (4.49:5.44:5.94))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_First_Buf_6_0_a2\[97\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.94:2.35:2.56) (1.87:2.27:2.48))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.37:5.31:5.79) (4.47:5.43:5.92))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_First_Buf_6_0_a2\[71\])
 (DELAY
  (ABSOLUTE
     (PORT A (9.05:10.97:11.98) (8.79:10.66:11.64))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.37:5.30:5.79) (4.47:5.43:5.92))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1")
 (INSTANCE U2\/Data_Second_Buf\[47\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.41:5.35:5.84) (4.51:5.47:5.97))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[79\])
 (DELAY
  (ABSOLUTE
     (PORT D (11.91:14.44:15.77) (11.34:13.76:15.02))
     (PORT CLK (4.41:5.35:5.84) (4.51:5.47:5.97))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.34:5.26:5.74) (4.43:5.37:5.86))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "INV")
 (INSTANCE AFLSDF_INV_0)
 (DELAY
  (ABSOLUTE
     (PORT A (0.0:0.0:0.0) (0.0:0.0:0.0))
     (IOPATH A Y (0.0:0.0:0.0) (0.0:0.0:0.0))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[48\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.45:5.40:5.90) (4.52:5.49:5.99))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[37\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.34:5.26:5.74) (4.42:5.37:5.86))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[70\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.38:5.31:5.80) (4.47:5.42:5.91))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.94:2.35:2.56) (1.87:2.27:2.48))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_First_Buf_6_0_a2\[9\])
 (DELAY
  (ABSOLUTE
     (PORT A (2.32:2.81:3.07) (2.19:2.66:2.90))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.41:5.35:5.85) (4.50:5.46:5.96))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[109\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
     (PORT CLK (4.31:5.23:5.71) (4.43:5.38:5.87))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.33:5.25:5.74) (4.42:5.36:5.85))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SE

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