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📄 lcd_top_ba.sdf

📁 基于FPGA的LCD1602驱动
💻 SDF
📖 第 1 页 / 共 5 页
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12345 
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[69\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
     (PORT CLK (4.41:5.35:5.84) (4.51:5.47:5.97))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.28:5.20:5.67) (4.38:5.31:5.80))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "MX2")
 (INSTANCE U2\/DB8_13_i\[1\])
 (DELAY
  (ABSOLUTE
     (PORT A (3.98:4.83:5.28) (3.75:4.55:4.97))
     (IOPATH A Y (3.06:3.76:4.24) (3.12:3.83:4.32))
     (PORT B (6.05:7.33:8.01) (5.58:6.77:7.39))
     (IOPATH B Y (3.15:3.88:4.37) (3.08:3.78:4.27))
     (PORT S (6.93:8.41:9.18) (6.42:7.79:8.51))
     (IOPATH S Y (2.58:3.36:3.79) (2.52:3.44:3.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[30\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
     (PORT CLK (4.35:5.27:5.75) (4.46:5.41:5.90))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.30:5.21:5.69) (4.39:5.33:5.81))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_7_0_a2\[43\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.39:5.33:5.82) (4.47:5.42:5.92))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "IOIN_IB")
 (INSTANCE rst_pad\/U0\/U1)
 (DELAY
  (ABSOLUTE
     (PORT YIN (0.00:0.00:0.00) (0.00:0.00:0.00))
     (IOPATH YIN Y (0.23:0.29:0.32) (0.22:0.26:0.30))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[33\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.37:5.30:5.78) (4.45:5.40:5.90))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2A")
 (INSTANCE U2\/un1_Data_Second_Buf_2_sqmuxa_0_a2\[0\])
 (DELAY
  (ABSOLUTE
     (PORT A (2.23:2.70:2.95) (2.09:2.53:2.77))
     (IOPATH A Y (2.51:3.08:3.48) (2.89:3.55:4.01))
     (PORT B (5.49:6.65:7.27) (5.15:6.25:6.82))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE U2\/state\[5\])
 (DELAY
  (ABSOLUTE
     (PORT D (10.51:12.75:13.92) (9.96:12.09:13.19))
     (PORT CLK (4.53:5.49:6.00) (4.63:5.62:6.14))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (11.64:14.12:15.41) (11.07:13.43:14.66))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_First_Buf_6_0_a2\[49\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.39:5.33:5.82) (4.47:5.42:5.92))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[43\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.47:5.43:5.93) (4.57:5.54:6.05))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.33:5.26:5.74) (4.42:5.36:5.85))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "BUFF")
 (INSTANCE rst_pad_1)
 (DELAY
  (ABSOLUTE
     (PORT A (7.81:9.47:10.34) (7.36:8.93:9.75))
     (IOPATH A Y (2.51:3.08:3.48) (2.89:3.55:4.01))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[74\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.55:5.52:6.03) (4.62:5.60:6.12))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.39:5.33:5.82) (4.47:5.42:5.92))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[56\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
     (PORT CLK (4.52:5.48:5.98) (4.59:5.57:6.08))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.37:5.30:5.78) (4.46:5.41:5.91))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "AND2")
 (INSTANCE U2\/un1_disp_count_1_I_1)
 (DELAY
  (ABSOLUTE
     (PORT A (4.02:4.88:5.32) (3.70:4.48:4.90))
     (IOPATH A Y (2.63:3.23:3.65) (2.77:3.40:3.84))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.40:4.17:4.71))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[93\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.32:5.24:5.72) (4.43:5.38:5.87))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.97:2.39:2.61) (1.89:2.29:2.50))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[111\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.35:5.27:5.75) (4.46:5.41:5.90))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.40:5.34:5.83) (4.48:5.43:5.93))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_7_0_a2\[111\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.33:5.25:5.73) (4.42:5.36:5.85))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[57\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.41:5.35:5.84) (4.51:5.47:5.97))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.44:5.38:5.87) (4.51:5.47:5.98))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[11\])
 (DELAY
  (ABSOLUTE
     (PORT D (4.44:5.38:5.88) (4.53:5.50:6.00))
     (PORT CLK (4.41:5.35:5.84) (4.51:5.47:5.97))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.30:5.21:5.69) (4.39:5.33:5.82))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (2.90:3.56:4.02))
     (SETUP (negedge D) (posedge CLK) (3.09:3.80:4.28))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[76\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.33:5.25:5.74) (4.42:5.36:5.86))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE U2\/disp_count\[3\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.41:5.35:5.84) (4.50:5.46:5.96))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (13.01:15.78:17.23) (11.71:14.20:15.51))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (2.90:3.56:4.02))
     (SETUP (negedge D) (posedge CLK) (3.09:3.80:4.28))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_7_0_a2\[59\])
 (DELAY
  (ABSOLUTE
     (PORT A (12.33:14.95:16.32) (11.82:14.33:15.65))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.30:5.22:5.70) (4.41:5.35:5.84))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE U2\/DB8\[0\]\/U1)
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.45:5.39:5.89) (4.53:5.50:6.00))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (10.22:12.40:13.53) (9.50:11.52:12.58))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (2.90:3.56:4.02))
     (SETUP (negedge D) (posedge CLK) (3.09:3.80:4.28))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE U2\/DB8\[4\]\/U1)
 (DELAY
12345

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