lcd_top_ba.sdf

基于FPGA的LCD1602驱动

     (PORT A (6.52:7.91:8.64) (6.22:7.54:8.23))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.37:5.30:5.78) (4.45:5.40:5.90))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "AND3")
 (INSTANCE U1\/un6_count_1_I_34)
 (DELAY
  (ABSOLUTE
     (PORT A (7.07:8.57:9.36) (6.39:7.75:8.47))
     (IOPATH A Y (2.83:3.47:3.92) (2.50:3.07:3.47))
     (PORT B (6.51:7.89:8.62) (6.00:7.28:7.95))
     (IOPATH B Y (3.36:4.13:4.66) (3.27:4.01:4.53))
     (PORT C (8.99:10.90:11.90) (8.23:9.98:10.89))
     (IOPATH C Y (3.58:4.40:4.97) (3.45:4.24:4.79))
  )
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 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[72\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.45:5.40:5.90) (4.53:5.50:6.00))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
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 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[26\])
 (DELAY
  (ABSOLUTE
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     (PORT CLK (4.45:5.39:5.89) (4.53:5.50:6.00))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.36:5.29:5.77) (4.45:5.40:5.89))
  )
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 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
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     (WIDTH (negedge CLK) (2.80:3.22:3.22))
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     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
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     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
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 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[103\])
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  (ABSOLUTE
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     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.40:5.34:5.83) (4.48:5.43:5.93))
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 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
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     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "MX2")
 (INSTANCE U2\/state_ns_0_m2\[6\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.38:5.32:5.80) (4.49:5.44:5.94))
     (IOPATH A Y (3.06:3.76:4.24) (3.12:3.83:4.32))
     (PORT B (2.31:2.80:3.06) (2.18:2.64:2.88))
     (IOPATH B Y (3.15:3.88:4.37) (3.08:3.78:4.27))
     (PORT S (7.17:8.69:9.49) (6.46:7.84:8.56))
     (IOPATH S Y (2.58:3.36:3.79) (2.52:3.44:3.88))
  )
 )
 )
 (CELL
 (CELLTYPE "PLL")
 (INSTANCE U1\/U1\/Core)
 (DELAY
  (ABSOLUTE
     (PORT CLKA (7.20:8.73:9.53) (6.89:8.35:9.12))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[53\])
 (DELAY
  (ABSOLUTE
     (PORT D (2.00:2.42:2.65) (1.93:2.34:2.55))
     (PORT CLK (4.44:5.39:5.89) (4.53:5.50:6.00))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.30:5.22:5.70) (4.40:5.33:5.82))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[52\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.38:5.31:5.80) (4.48:5.44:5.94))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.30:5.21:5.69) (4.39:5.33:5.82))
  )
 )
 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[94\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.94:2.35:2.56) (1.85:2.25:2.45))
     (PORT CLK (4.32:5.24:5.72) (4.44:5.39:5.88))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.36:5.29:5.77) (4.46:5.41:5.91))
  )
 )
 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[17\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.46:5.41:5.91) (4.55:5.52:6.03))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.94:2.35:2.56) (1.87:2.27:2.48))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "OA1A")
 (INSTANCE U2\/disp_count_9_i\[1\])
 (DELAY
  (ABSOLUTE
     (PORT A (11.25:13.64:14.89) (10.73:13.01:14.21))
     (IOPATH A Y (5.30:6.51:7.35) (3.94:4.84:5.46))
     (PORT B (8.50:10.31:11.26) (7.86:9.53:10.41))
     (IOPATH B Y (4.90:6.03:6.80) (3.27:4.01:4.53))
     (PORT C (1.85:2.24:2.45) (1.76:2.14:2.34))
     (IOPATH C Y (2.14:2.63:2.97) (2.18:2.68:3.02))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE U2\/disp_count\[1\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.41:5.35:5.84) (4.51:5.47:5.97))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (15.76:19.11:20.86) (14.14:17.14:18.72))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (2.90:3.56:4.02))
     (SETUP (negedge D) (posedge CLK) (3.09:3.80:4.28))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[75\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.63:5.61:6.13) (4.71:5.71:6.24))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (2.08:2.52:2.75) (2.01:2.44:2.66))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
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 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[96\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
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  )
 )
 (TIMINGCHECK 
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     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
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     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[91\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.50:5.46:5.96) (4.57:5.54:6.05))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[86\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.94:2.35:2.56) (1.87:2.27:2.48))
     (PORT CLK (4.36:5.28:5.77) (4.47:5.42:5.92))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.36:5.29:5.77) (4.45:5.40:5.89))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OA1A")
 (INSTANCE U2\/disp_count_9_i\[2\])
 (DELAY
  (ABSOLUTE
     (PORT A (14.21:17.23:18.82) (13.57:16.46:17.97))
     (IOPATH A Y (5.30:6.51:7.35) (3.94:4.84:5.46))
     (PORT B (5.95:7.21:7.87) (5.44:6.60:7.21))
     (IOPATH B Y (4.90:6.03:6.80) (3.27:4.01:4.53))
     (PORT C (1.97:2.39:2.61) (1.91:2.31:2.52))
     (IOPATH C Y (2.14:2.63:2.97) (2.18:2.68:3.02))
  )
 )
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 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE U2\/DB8\[2\]\/U1)
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.45:5.39:5.89) (4.53:5.50:6.00))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (9.08:11.01:12.02) (8.38:10.17:11.10))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (2.90:3.56:4.02))
     (SETUP (negedge D) (posedge CLK) (3.09:3.80:4.28))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
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     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
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 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[87\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
     (PORT CLK (4.38:5.31:5.80) (4.48:5.44:5.94))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.32:5.23:5.71) (4.42:5.36:5.86))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[32\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.52:5.48:5.98) (4.59:5.57:6.08))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.39:5.33:5.82) (4.47:5.42:5.92))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[102\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.63:5.61:6.13) (4.71:5.71:6.24))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (2.08:2.52:2.75) (2.01:2.44:2.66))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[32\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.45:5.40:5.90) (4.52:5.49:5.99))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL