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📄 lcd_top_ba.sdf

📁 基于FPGA的LCD1602驱动
💻 SDF
📖 第 1 页 / 共 5 页
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 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[110\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.38:5.31:5.80) (4.48:5.44:5.93))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.37:5.30:5.79) (4.46:5.40:5.90))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[71\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
     (PORT CLK (4.31:5.23:5.71) (4.43:5.37:5.87))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.28:5.20:5.67) (4.38:5.31:5.80))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[65\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.83:2.23:2.43))
     (PORT CLK (4.41:5.35:5.84) (4.51:5.47:5.97))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.44:5.38:5.87) (4.51:5.47:5.98))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/DB8_13_i_a2_0_s\[3\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.88:2.28:2.49) (1.82:2.20:2.41))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (2.39:2.90:3.17) (2.24:2.72:2.97))
     (IOPATH B Y (2.77:3.40:3.84) (3.48:4.28:4.83))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[37\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.97:2.39:2.61) (1.89:2.29:2.50))
     (PORT CLK (4.45:5.39:5.89) (4.53:5.50:6.00))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.33:5.25:5.73) (4.44:5.38:5.88))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[110\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.63:5.61:6.13) (4.71:5.71:6.24))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (2.08:2.52:2.75) (2.01:2.44:2.66))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "MX2")
 (INSTANCE U2\/DB8\[0\]\/U0)
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.58:4.40:4.97) (3.33:4.09:4.62))
     (PORT B (1.92:2.33:2.54) (1.83:2.23:2.43))
     (IOPATH B Y (3.15:3.88:4.37) (3.08:3.78:4.27))
     (PORT S (7.07:8.57:9.36) (6.50:7.88:8.61))
     (IOPATH S Y (2.58:3.36:3.79) (2.52:3.44:3.88))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[101\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.36:5.28:5.77) (4.46:5.41:5.91))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (6.75:8.19:8.94) (6.44:7.81:8.52))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[56\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.36:5.28:5.77) (4.44:5.39:5.88))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_First_Buf_6_0_a2\[57\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.39:5.33:5.82) (4.47:5.42:5.92))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[16\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
     (PORT CLK (4.44:5.39:5.89) (4.53:5.50:6.00))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.30:5.21:5.69) (4.39:5.33:5.82))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[60\])
 (DELAY
  (ABSOLUTE
     (PORT D (9.85:11.95:13.05) (9.41:11.41:12.46))
     (PORT CLK (4.41:5.35:5.84) (4.51:5.47:5.97))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.37:5.30:5.79) (4.45:5.40:5.89))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[74\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.43:5.37:5.86) (4.51:5.47:5.97))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_Second_Buf\[83\])
 (DELAY
  (ABSOLUTE
     (PORT D (9.48:11.50:12.55) (9.00:10.92:11.92))
     (PORT CLK (4.35:5.27:5.75) (4.46:5.41:5.90))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.30:5.22:5.70) (4.40:5.33:5.82))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_7_0_a2\[63\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.30:5.21:5.69) (4.41:5.34:5.83))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_First_Buf_6_i_a2\[19\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.40:5.33:5.82) (4.48:5.43:5.93))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1C1")
 (INSTANCE U1\/count\[6\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
     (PORT CLK (4.46:5.41:5.90) (4.55:5.52:6.02))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT CLR (10.15:12.31:13.44) (9.20:11.16:12.18))
     (IOPATH CLR Q () (2.87:3.53:3.99))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (WIDTH (posedge CLR) (1.92:2.21:2.21))
     (RECOVERY (negedge CLR) (posedge CLK) (1.60:1.97:2.22))
     (HOLD (negedge CLR) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "MX2")
 (INSTANCE U1\/clk_BUF\/U0)
 (DELAY
  (ABSOLUTE
     (PORT A (4.53:5.49:5.99) (4.63:5.62:6.13))
     (IOPATH A Y (3.58:4.40:4.97) (3.33:4.09:4.62))
     (PORT B (2.10:2.54:2.77) (2.03:2.46:2.69))
     (IOPATH B Y (3.15:3.88:4.37) (3.08:3.78:4.27))
     (PORT S (9.54:11.57:12.64) (9.07:11.00:12.01))
     (IOPATH S Y (2.58:3.36:3.79) (2.52:3.44:3.88))
  )
 )
 )
 (CELL
 (CELLTYPE "AX1C")
 (INSTANCE U1\/un6_count_1_I_9)
 (DELAY
  (ABSOLUTE
     (PORT A (11.08:13.44:14.68) (10.58:12.83:14.01))
     (IOPATH A Y (3.57:6.24:7.05) (3.29:4.14:4.67))
     (PORT B (9.91:12.02:13.12) (9.24:11.20:12.23))
     (IOPATH B Y (3.65:6.42:7.24) (3.45:4.42:4.98))
     (PORT C (2.64:3.21:3.50) (2.43:2.95:3.22))
     (IOPATH C Y (1.85:3.23:3.65) (2.14:2.68:3.02))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_7_0_a2\[71\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.39:5.33:5.81) (4.48:5.43:5.93))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2")
 (INSTANCE U2\/Data_Second_Buf_7_i_a2\[82\])
 (DELAY
  (ABSOLUTE
     (PORT A (4.37:5.30:5.78) (4.46:5.41:5.90))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_Second_Buf_7_0_a2\[95\])
 (DELAY
  (ABSOLUTE
     (PORT A (1.92:2.33:2.54) (1.85:2.25:2.45))
     (IOPATH A Y (3.18:3.91:4.41) (3.40:4.17:4.71))
     (PORT B (4.39:5.33:5.81) (4.48:5.43:5.93))
     (IOPATH B Y (2.19:2.69:3.04) (2.08:2.55:2.88))
  )
 )
 )
 (CELL
 (CELLTYPE "OR2A")
 (INSTANCE U2\/un1_Data_First_Buf_1_sqmuxa_0_a2)
 (DELAY
  (ABSOLUTE
     (PORT A (1.85:2.24:2.45) (1.76:2.14:2.34))
     (IOPATH A Y (1.96:2.40:2.71) (2.73:3.36:3.79))
     (PORT B (8.27:10.03:10.95) (7.76:9.42:10.28))
     (IOPATH B Y (3.18:3.91:4.41) (3.50:4.30:4.85))
  )
 )
 )
 (CELL
 (CELLTYPE "DFN1E0")
 (INSTANCE U2\/Data_First_Buf\[48\])
 (DELAY
  (ABSOLUTE
     (PORT D (1.92:2.33:2.54) (1.85:2.25:2.45))
     (PORT CLK (4.37:5.30:5.79) (4.47:5.42:5.91))
     (IOPATH CLK Q (3.13:3.84:4.34) (3.97:4.88:5.50))
     (PORT E (4.30:5.21:5.69) (4.40:5.33:5.82))
  )
 )
 (TIMINGCHECK 
     (SETUP (posedge D) (posedge CLK) (3.09:3.80:4.28))
     (SETUP (negedge D) (posedge CLK) (2.90:3.56:4.02))
     (HOLD (posedge D) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge D) (posedge CLK) (0.00:0.00:0.00))
     (WIDTH (posedge CLK) (3.10:3.56:3.56))
     (WIDTH (negedge CLK) (2.80:3.22:3.22))
     (SETUP (posedge E) (posedge CLK) (2.34:2.88:3.25))
     (SETUP (negedge E) (posedge CLK) (3.28:4.02:4.54))
     (HOLD (posedge E) (posedge CLK) (0.00:0.00:0.00))
     (HOLD (negedge E) (posedge CLK) (0.00:0.00:0.00))
 )
 )
 (CELL
 (CELLTYPE "NOR2A")
 (INSTANCE U2\/Data_First_Buf_6_0_a2\[89\])
 (DELAY
  (ABSOLUTE

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