c8051.vhd

8051 mega core porocesssor vhdl source code

                     sfrwe        => int_sfrwe
                     );
   
   
      -----------------------------------------------------------------
      -- Clock Control Unit
      -----------------------------------------------------------------
      U_CLKCTRL : CLOCK_CONTROL
            port map (
                     clk          => clk,
                     reset        => reset,
                     cycle        => cycle,
                     phase        => phase,
                     parcycle     => parcycle,
                     rsto         => rst,
                     smod         => smod,
                     sfrdatai     => sfrdatabus,
                     sfrdataclk   => sfrdataclk,
                     sfraddr      => ramsfraddr(6 downto 0),
                     sfrwe        => int_sfrwe
                     );
   
   
      -----------------------------------------------------------------
      -- Control Processor Unit
      -----------------------------------------------------------------
      U_CPU : CONTROL_UNIT
            port map (
                     clk          => clk,
                     rst          => rst,
                     intreq       => intreq,
                     debugreq     => debugreq,
                     debugprog    => debugprog,
                     debugprogff  => debugprogff,
                     debugstep    => debugstep,
                     debugstepff  => debugstepff,
                     debugmode    => debugmode,
                     instr        => instr,
                     cycle        => cycle,
                     nrcycles     => nrcycles,
                     phase        => phase,
                     parcycle     => parcycle,
                     pcince       => pcince,
                     codefetche   => codefetche,
                     codefetcheff => codefetcheff,
                     datafetche   => datafetche,
                     rmwinstr     => rmwinstr,
                     intack       => intack,
                     intret       => intret,
                     intcall      => intcall,
                     memdatai     => memdatai
                     );
   
   
      -----------------------------------------------------------------
      -- Interrupt Service Routine Unit
      -----------------------------------------------------------------
      U_ISR : ISR
            port map (
                     clk          => clk,
                     rst          => rst,
                     phase        => phase,
                     instr        => instr,
                     debugmode    => debugmode,
                     tf0          => tf0,
                     tf1          => tf1,
                     riti         => riti,
                     ie0          => ie0,
                     ie1          => ie1,
                     intret       => intret,
                     intack       => intack,
                     intvect      => intvect,
                     intreq       => intreq,
                     t0ack        => t0ack,
                     t1ack        => t1ack,
                     int0ack      => int0ack,
                     int1ack      => int1ack,
                     sfrdatai     => sfrdatabus,
                     sfrdataisr   => sfrdataisr,
                     sfraddr      => ramsfraddr(6 downto 0),
                     sfrwe        => int_sfrwe
                     );
   
   
      -----------------------------------------------------------------
      -- External Memory Control Unit
      -----------------------------------------------------------------
      U_MEMCTRL : MEMORY_CONTROL
            port map (
                     clk          => clk,
                     rst          => rst,
                     ea           => ea,
                     instr        => instr,
                     cycle        => cycle,
                     phase        => phase,
                     codefetche   => codefetche,
                     datafetche   => datafetche,
                     intcall      => intcall,
                     pcince       => pcince,
                     accreg       => accreg,
                     bitvalue     => bitvalue,
                     cdjump       => cdjump,
                     cyflag       => cyflag,
                     intvect      => intvect,
                     p2reg        => p2reg, 
                     debugstepff  => debugstepff,
                     debugmode    => debugmode,
                     flushff      => flushff,
                     ramdatai     => ramdatai,
                     intromacs    => intromacs,
                     pclreg       => pclreg,
                     pchreg       => pchreg,
                     memdatai     => memdatai,
                     memaddr      => memaddr,
                     memwr        => memwr,
                     memrd        => memrd,
                     memp0acs     => memp0acs,
                     memp2acs     => memp2acs,
                     addrdatasel  => addrdatasel,
                     romoe        => int_romoe,
                     psen         => psen,
                     ale          => ale,
                     sfrdatai     => sfrdatabus,
                     sfrdatamcu   => sfrdatamcu,
                     sfraddr      => ramsfraddr(6 downto 0),
                     sfrwe        => int_sfrwe
                     );
                     
      -----------------------------------------------------------------
      -- OCI Unit
      -----------------------------------------------------------------
      U_OCI : OCI
            port map (
                     clk          => clk,
                     rst          => rst,
                     cycle        => cycle,
                     nrcycles     => nrcycles,
                     phase        => phase,
                     codefetche   => codefetche,
                     codefetcheff => codefetcheff,
                     datafetche   => datafetche,
                     flushff      => flushff,
                     memdatai     => memdatai,
                     debugreq     => debugreq,
                     debugstep    => debugstep,
                     debugprog    => debugprog,
                     debugstepff  => debugstepff,
                     debugprogff  => debugprogff,
                     debugmode    => debugmode,
                     debugack     => debugack,
                     flush        => flush,
                     fetch        => fetch
                     );

   
   
      -----------------------------------------------------------------
      -- Port registers unit
      -----------------------------------------------------------------
      U_PORTS : PORTS
            port map (
                     clk          => clk,
                     rst          => rst,
                     p0i          => p0i,
                     p1i          => p1i,
                     p2i          => p2i,
                     p3i          => p3i,
                     txd          => txd,
                     rxdo         => rxdo,
                     rmwinstr     => rmwinstr,
                     romdatai     => romdatai,
                     memdatai     => memdatai,
                     memdatao     => accreg,
                     memaddr      => memaddr,
                     memwr        => memwr,
                     memrd        => memrd,
                     addrdatasel  => addrdatasel,
                     memp0acs     => memp0acs,
                     memp2acs     => memp2acs,
                     romoe        => int_romoe,
                     p2reg        => p2reg,
                     p0o          => int_p0o,
                     p1o          => int_p1o,
                     p2o          => int_p2o,
                     p3o          => int_p3o,
                     sfrdatai     => sfrdatabus,
                     sfrdataports => sfrdataports,
                     sfraddr      => ramsfraddr(6 downto 0),
                     sfrwe        => int_sfrwe
                     );
   
   
      -----------------------------------------------------------------
      -- 256B Data Memory and Special Function Registers Control Unit
      -----------------------------------------------------------------
      U_RAMSFRCTRL : RAM_SFR_CONTROL
            port map (  
                     clk          => clk,
                     rst          => rst,
                     instr        => instr,
                     cycle        => cycle,
                     phase        => phase,
                     regsbank     => regsbank,
                     sfrdatai     => sfrdatabus,
                     pclreg       => pclreg,
                     pchreg       => pchreg,
                     memdatai     => memdatai,
                     databus      => databus,
                     ramsfraddr   => ramsfraddr,
                     ramdatai     => ramdatai,
                     ramdatao     => intramdatao,
                     ramwe        => ramwe,
                     ramoe        => ramoe,
                     sfrdataalu   => sfrdataalu,
                     sfrdataclk   => sfrdataclk,
                     sfrdataisr   => sfrdataisr,
                     sfrdatamcu   => sfrdatamcu,
                     sfrdataports => sfrdataports,
                     sfrdataser   => sfrdataser,
                     sfrdatatim   => sfrdatatim,
                     sfrdataext   => sfrdataext,
                     sfrwe        => int_sfrwe,
                     sfroe        => int_sfroe
                     );
   
   
      -----------------------------------------------------------------
      -- Serial Interface Unit 
      -----------------------------------------------------------------
      U_SERIAL : SERIAL
            port map (
                     clk          => clk,
                     rst          => rst,
                     cycle        => cycle,
                     phase        => phase,
                     rxdi         => rxdi,
                     t1ov         => t1ov,
                     smod         => smod,                                        
                     riti         => riti,
                     rxdo         => rxdo,
                     txd          => txd,
                     sfrdatai     => sfrdatabus,
                     sfrdataser   => sfrdataser,
                     sfraddr      => ramsfraddr(6 downto 0),
                     sfrwe        => int_sfrwe
                     );
   
   
      -----------------------------------------------------------------
      -- Timer/Counter 0 and 1
      -----------------------------------------------------------------
      U_TIMER_0_1 : TIMER_0_1
            port map (
                     clk          => clk,
                     rst          => rst,
                     cycle        => cycle,
                     phase        => phase,
                     t0           => t0,
                     t1           => t1,
                     t0ack        => t0ack,
                     t1ack        => t1ack,
                     int0         => int0,
                     int1         => int1,
                     int0ack      => int0ack,
                     int1ack      => int1ack,
                     tf0          => tf0,
                     tf1          => tf1,
                     ie0          => ie0,
                     ie1          => ie1,
                     t1ov         => t1ov,
                     sfrdatai     => sfrdatabus,
                     sfrdatatim   => sfrdatatim,
                     sfraddr      => ramsfraddr(6 downto 0),
                     sfrwe        => int_sfrwe
                     );
   
   
   end STRUCTURAL;
--*******************************************************************--