c8051.vhd

8051 mega core porocesssor vhdl source code

      -- Aritmetic Logic Unit
      -----------------------------------------------------------------
      signal accreg            : STD_LOGIC_VECTOR(7 downto 0);
      signal regsbank          : STD_LOGIC_VECTOR(1 downto 0);
      signal bitvalue          : STD_LOGIC;
      signal cdjump            : STD_LOGIC;
      signal cyflag            : STD_LOGIC;
      signal sfrdatabus        : STD_LOGIC_VECTOR(7 downto 0);
      signal sfrdataalu        : STD_LOGIC_VECTOR(7 downto 0);
   
      -----------------------------------------------------------------
      -- Clock Control Unit signals
      -----------------------------------------------------------------
      signal rst               : STD_LOGIC;
      signal smod              : STD_LOGIC;
      signal sfrdataclk        : STD_LOGIC_VECTOR(7 downto 0); 
   
      -----------------------------------------------------------------
      -- Control Processor Unit signals
      -----------------------------------------------------------------
      signal instr             : STD_LOGIC_VECTOR(7 downto 0);
      signal cycle             : INTEGER range 1 to 8;
      signal nrcycles          : INTEGER range 1 to 8;
      signal phase             : INTEGER range 1 to 6;
      signal parcycle          : STD_LOGIC;
      signal codefetche        : STD_LOGIC;
      signal datafetche        : STD_LOGIC;
      signal rmwinstr          : STD_LOGIC;
      signal intack            : STD_LOGIC;
      signal intret            : STD_LOGIC;
      signal intcall           : STD_LOGIC;
      signal pcince            : STD_LOGIC;
   
      -----------------------------------------------------------------
      -- Interrupt Service Routine Unit signals
      -----------------------------------------------------------------
      signal intvect           : STD_LOGIC_VECTOR(2 downto 0);
      signal intreq            : STD_LOGIC;
      signal sfrdataisr        : STD_LOGIC_VECTOR(7 downto 0);
      signal t0ack             : STD_LOGIC;
      signal t1ack             : STD_LOGIC;
      signal int0ack           : STD_LOGIC;
      signal int1ack           : STD_LOGIC;
   
      signal ie0               : STD_LOGIC;
      signal ie1               : STD_LOGIC;
      signal t0                : STD_LOGIC;
      signal t1                : STD_LOGIC;
   
      -----------------------------------------------------------------
      -- Memory Control Unit signals
      -----------------------------------------------------------------
      signal intromacs         : STD_LOGIC;
      signal pclreg            : STD_LOGIC_VECTOR(7 downto 0);
      signal pchreg            : STD_LOGIC_VECTOR(7 downto 0);
      signal memaddr           : STD_LOGIC_VECTOR(15 downto 0);
      signal memwr             : STD_LOGIC;
      signal memrd             : STD_LOGIC;
      signal memp0acs          : STD_LOGIC;
      signal memp2acs          : STD_LOGIC;
      signal addrdatasel       : STD_LOGIC;
      signal int_romoe         : STD_LOGIC;
      signal sfrdatamcu        : STD_LOGIC_VECTOR(7 downto 0);
      signal flushff           : STD_LOGIC;
      
      -----------------------------------------------------------------
      -- OCI Unit signals
      -----------------------------------------------------------------
      signal codefetcheff      : STD_LOGIC;
      signal debugstepff       : STD_LOGIC;
      signal debugprogff       : STD_LOGIC;
      signal debugmode         : STD_LOGIC;

      -----------------------------------------------------------------
      -- 256B Data Memory and Special Function Registers Control Unit
      ----------------------------------------------------------------- 
      signal databus           : STD_LOGIC_VECTOR(7 downto 0);
      signal ramsfraddr        : STD_LOGIC_VECTOR(7 downto 0);
      signal intramdatao       : STD_LOGIC_VECTOR(7 downto 0);
      signal int_sfrwe         : STD_LOGIC;
      signal int_sfroe         : STD_LOGIC;     
      signal sfrdataext        : STD_LOGIC_VECTOR(7 downto 0);
   
      -----------------------------------------------------------------
      -- Serial Interface Unit signals 
      -----------------------------------------------------------------
      signal txd               : STD_LOGIC;
      signal rxdo              : STD_LOGIC;
      signal riti              : STD_LOGIC;
      signal sfrdataser        : STD_LOGIC_VECTOR(7 downto 0);
      signal t1ov              : STD_LOGIC;     
      signal rxdi              : STD_LOGIC;
   
      -----------------------------------------------------------------
      -- Timer/Counter 0 and 1
      ----------------------------------------------------------------- 
      signal tf0               : STD_LOGIC;
      signal tf1               : STD_LOGIC;
      signal sfrdatatim        : STD_LOGIC_VECTOR(7 downto 0);
      signal int0              : STD_LOGIC;
      signal int1              : STD_LOGIC;
   
      -----------------------------------------------------------------
      -- Pull-up and pull-down drivers
      -----------------------------------------------------------------
      signal gnd             : STD_LOGIC;
      signal vcc             : STD_LOGIC;
   
   begin
   
   
   --------------------------------------------------------------------
   -- Port alternate functions mapping
   --------------------------------------------------------------------
   -- Port 3 : input      : output
   ------------------------------------
   -- p3(0)  : rxd        : 
   -- p3(1)  :            : txd
   -- p3(2)  : int0       : 
   -- p3(3)  : int1       :
   -- p3(4)  : t0         :
   -- p3(5)  : t1         :
   -- p3(6)  :            : wr
   -- p3(7)  :            : rd
   --------------------------------------------------------------------
   
   --------------------------------------------------------------------
   -- Pull-up and pull-down drivers
   --------------------------------------------------------------------
   gnd_hand : gnd <= '0';
   vcc_hand : vcc <= '1';
   
   
   -----------------------------------------------------------------
   -- Ports output drivers
   -----------------------------------------------------------------
   p0o_drv : p0o <= int_p0o;
   p1o_drv : p1o <= int_p1o;
   p2o_drv : p2o <= int_p2o;
   p3o_drv : p3o <= int_p3o;
   
   
   --------------------------------------------------------------------
   -- Accumulator output
   --------------------------------------------------------------------
   acc_drv : 
   --------------------------------------------------------------------
      acc <= accreg;
   
   --------------------------------------------------------------------
   -- Internal program memory interface
   -- Address bus output
   --------------------------------------------------------------------
   romaddr_drv : 
   --------------------------------------------------------------------
      romaddr <= memaddr(13 downto 0);
   
   
   --------------------------------------------------------------------
   -- Internal data memory interface
   -- Data bus output
   --------------------------------------------------------------------
   ramdatao_drv : 
   --------------------------------------------------------------------
      ramdatao <= intramdatao;
   
   
   --------------------------------------------------------------------
   -- External SFR interface
   -- Data bus input
   --------------------------------------------------------------------
   sfrdataext_hand : 
   --------------------------------------------------------------------
      sfrdataext <= sfrdatai;
   
   
   --------------------------------------------------------------------
   -- Internal data memory interface
   -- Address bus output
   --------------------------------------------------------------------
   ramaddr_drv :
   --------------------------------------------------------------------
      ramaddr <= ramsfraddr;
   
   
   --------------------------------------------------------------------
   -- External Special function register interface
   -- Data bus output
   --------------------------------------------------------------------
   sfrdatao_drv : 
   --------------------------------------------------------------------
      sfrdatao <= sfrdatabus; -- sfrdatao from ALU
   
   
   --------------------------------------------------------------------
   -- External Special Function register interface
   -- Address bus output
   --------------------------------------------------------------------
   sfraddr_drv : 
   --------------------------------------------------------------------
      sfraddr <= ramsfraddr(6 downto 0);
   
   
   --------------------------------------------------------------------
   -- External Special function register interface
   -- Write enable output
   --------------------------------------------------------------------
   sfrwe_drv :
   --------------------------------------------------------------------
      sfrwe <= int_sfrwe;
   
   
   --------------------------------------------------------------------
   -- External Special function register interface
   -- Output enable output
   --------------------------------------------------------------------
   sfroe_drv :
   --------------------------------------------------------------------
      sfroe <= int_sfroe;
   
   
   --------------------------------------------------------------------
   -- External interrupt inputs
   --------------------------------------------------------------------    
   int0_hand :
   --------------------------------------------------------------------    
      int0 <= p3i(2);
   --------------------------------------------------------------------    
   int1_hand :
   --------------------------------------------------------------------    
      int1 <= p3i(3);
   
   
   --------------------------------------------------------------------
   -- Timer_0_1 input
   --------------------------------------------------------------------
   t0_hand : 
   --------------------------------------------------------------------
      t0 <= p3i(4);
   --------------------------------------------------------------------
   t1_hand : 
   --------------------------------------------------------------------
      t1 <= p3i(5);
   
   
   --------------------------------------------------------------------
   -- Serial port receiver
   --------------------------------------------------------------------
   rxdi_hand : 
   --------------------------------------------------------------------
      rxdi <= p3i(0);
   
   
   -------------------------------------------------------------------
   -- ROM OE
   --------------------------------------------------------------------
   romoe_hand :
   --------------------------------------------------------------------
      romoe <= int_romoe;
      
   
      -----------------------------------------------------------------
      -- Aritmetic Logic Unit
      -----------------------------------------------------------------
      U_ALU : ALU
            port map (
                     clk          => clk,
                     rst          => rst,
                     instr        => instr,
                     cycle        => cycle,
                     phase        => phase,
                     memdatai     => memdatai,
                     databus      => databus,
                     accreg       => accreg,
                     regsbank     => regsbank,
                     bitvalue     => bitvalue,
                     cdjump       => cdjump,
                     cyflag       => cyflag,
                     sfraddr      => ramsfraddr(6 downto 0),
                     sfrdatao     => sfrdatabus,
                     sfrdataalu   => sfrdataalu,