📄 c8051.vhd
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cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
codefetche : in STD_LOGIC; -- Opcode fetch enable
datafetche : in STD_LOGIC; -- Data fertch enable
--bufffetche : in STD_LOGIC; -- Buffer fetch enable
intcall : in STD_LOGIC; -- Interrupt call routine
pcince : in STD_LOGIC;
-- ALU input signals
accreg : in STD_LOGIC_VECTOR(7 downto 0);
bitvalue : in STD_LOGIC;
cdjump : in STD_LOGIC;
cyflag : in STD_LOGIC;
-- ISR input signals
intvect : in STD_LOGIC_VECTOR(2 downto 0);
-- Ports input signals
p2reg : in STD_LOGIC_VECTOR(7 downto 0);
-- OCI control signals
debugstepff : in STD_LOGIC;
debugmode : in STD_LOGIC;
flushff : out STD_LOGIC;
-- Internal Data Memory input
ramdatai : in STD_LOGIC_VECTOR(7 downto 0);
-- CPU output signals
intromacs : out STD_LOGIC; -- Internal ROM access
-- RAM_SFR control outputs
pclreg : out STD_LOGIC_VECTOR(7 downto 0);
pchreg : out STD_LOGIC_VECTOR(7 downto 0);
-- Memory interface
memdatai : in STD_LOGIC_VECTOR( 7 downto 0);
memaddr : out STD_LOGIC_VECTOR(15 downto 0);
memwr : out STD_LOGIC; -- Memory write enable
memrd : out STD_LOGIC; -- Memory read enable
memp0acs : out STD_LOGIC; -- External memory accsess P0
memp2acs : out STD_LOGIC; -- External memory accsess P2
addrdatasel : out STD_LOGIC; -- Address/Data bus select
romoe : out STD_LOGIC; -- Int. program memory enable
psen : out STD_LOGIC; -- Ext. Program Store Enable
ale : out STD_LOGIC; -- Ext. Address Latch Enable
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatamcu : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrwe : in STD_LOGIC
);
end component;
-----------------------------------------------------------------
-- OCI unit
-----------------------------------------------------------------
component OCI
port (
-- Control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Internal reset input
-- CPU input signals
cycle : in INTEGER range 1 to 8;
nrcycles : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
codefetche : in STD_LOGIC;
codefetcheff : in STD_LOGIC;
datafetche : in STD_LOGIC;
-- memory control input signal
flushff : in STD_LOGIC;
-- program memory input
memdatai : in STD_LOGIC_VECTOR(7 downto 0);
-- OCI inputs
debugreq : in STD_LOGIC; -- Debug Request
debugstep : in STD_LOGIC; -- Debug Step
debugprog : in STD_LOGIC; -- Debugger program
-- OCI outputs
debugstepff : out STD_LOGIC;
debugprogff : out STD_LOGIC;
debugmode : out STD_LOGIC;
debugack : out STD_LOGIC; -- Debug Acknowledge
flush : out STD_LOGIC;
fetch : out STD_LOGIC
);
end component;
-----------------------------------------------------------------
-- Port registers unit
-----------------------------------------------------------------
component PORTS
port (
-- Control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- Port inputs
p0i : in STD_LOGIC_VECTOR(7 downto 0);
p1i : in STD_LOGIC_VECTOR(7 downto 0);
p2i : in STD_LOGIC_VECTOR(7 downto 0);
p3i : in STD_LOGIC_VECTOR(7 downto 0);
-- Alternate function input
txd : in STD_LOGIC; -- serial async. transmitter
rxdo : in STD_LOGIC; -- serial sync. transmitter
-- CPU control signals
rmwinstr : in STD_LOGIC; -- Read-Modify-Write Instr.
-- Memory interface
romdatai : in STD_LOGIC_VECTOR( 7 downto 0);
memdatai : out STD_LOGIC_VECTOR( 7 downto 0);
memdatao : in STD_LOGIC_VECTOR( 7 downto 0);
memaddr : in STD_LOGIC_VECTOR(15 downto 0);
memwr : in STD_LOGIC; -- External data memory write
memrd : in STD_LOGIC; -- External data memory read
addrdatasel : in STD_LOGIC; -- Address/Data bus select
memp0acs : in STD_LOGIC; -- Address/Data - port reg.
memp2acs : in STD_LOGIC; -- Address - port reg. select
romoe : in STD_LOGIC; -- Int. program memory enabl
-- p2 register
p2reg : out STD_LOGIC_VECTOR(7 downto 0);
-- Port outputs
p0o : out STD_LOGIC_VECTOR(7 downto 0);
p1o : out STD_LOGIC_VECTOR(7 downto 0);
p2o : out STD_LOGIC_VECTOR(7 downto 0);
p3o : out STD_LOGIC_VECTOR(7 downto 0);
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataports : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrwe : in STD_LOGIC
);
end component;
-----------------------------------------------------------------
-- 256B Data Memory and Special Function Registers Control Unit
-----------------------------------------------------------------
component RAM_SFR_CONTROL
port (
-- Global control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- CPU input signals
instr : in STD_LOGIC_VECTOR(7 downto 0);
cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
-- RAM and SFR input signals
regsbank : in STD_LOGIC_VECTOR(1 downto 0);
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
-- Memory Control input signals
pclreg : in STD_LOGIC_VECTOR(7 downto 0);
pchreg : in STD_LOGIC_VECTOR(7 downto 0);
-- External/Internal ROM Memory interface
memdatai : in STD_LOGIC_VECTOR(7 downto 0);
-- Internal Data Bus
databus : out STD_LOGIC_VECTOR(7 downto 0);
-- RAM and SFR address bus
ramsfraddr : out STD_LOGIC_VECTOR(7 downto 0);
-- Data file interface
ramdatai : in STD_LOGIC_VECTOR(7 downto 0);
ramdatao : out STD_LOGIC_VECTOR(7 downto 0);
ramwe : out STD_LOGIC; -- Data file write enable
ramoe : out STD_LOGIC; -- Data file output enable
-- Special function register interface
sfrdataalu : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataclk : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataisr : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatamcu : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataports : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataser : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatatim : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataext : in STD_LOGIC_VECTOR(7 downto 0);
sfrwe : out STD_LOGIC; -- SFR write enable
sfroe : out STD_LOGIC -- SFR output enable
);
end component;
---------------------------------------------------------------
-- Serial Interface Unit
-----------------------------------------------------------------
component SERIAL
port (
-- Control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- CPU input signals
cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
rxdi : in STD_LOGIC; -- Serial receive data
t1ov : in STD_LOGIC; -- Timer 1 overflow output
smod : in STD_LOGIC; -- Baud rate Doubler
riti : out STD_LOGIC; -- Serial rec./tr. flag
-- Serial outputs
rxdo : out STD_LOGIC; -- Serial transmit data
txd : out STD_LOGIC; -- Serial transmit clock
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataser : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrwe : in STD_LOGIC );
end component;
--------------------------------------------------------------
-- Timer/Counter 0 and 1
-----------------------------------------------------------------
component TIMER_0_1
port (
-- Control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- CPU input signals
cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
-- Timers inputs
t0 : in STD_LOGIC; -- Timer 0 external input
t1 : in STD_LOGIC; -- Timer 1 external input
t0ack : in STD_LOGIC; -- Timer 0 int. acknowledge
t1ack : in STD_LOGIC; -- Timer 1 int. acknowledge
int0 : in STD_LOGIC; -- External interrupt 0 input
int1 : in STD_LOGIC; -- External interrupt 1 input
int0ack : in STD_LOGIC; -- External int0 acknowledge
int1ack : in STD_LOGIC; -- External int1 acknowledge
-- Timer interrupt flags
tf0 : out STD_LOGIC; -- Timer 0 overflow flag
tf1 : out STD_LOGIC; -- Timer 1 overflow flag
ie0 : out STD_LOGIC; -- Interrupt 0 edge detect
ie1 : out STD_LOGIC; -- Interrupt 1 edge detect
-- Timer outputs
t1ov : out STD_LOGIC; -- Timer 1 overflow output
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatatim : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrwe : in STD_LOGIC
);
end component;
-----------------------------------------------------------------
-- Ports output drivers
-----------------------------------------------------------------
signal memdatai : STD_LOGIC_VECTOR(7 downto 0);
signal p2reg : STD_LOGIC_VECTOR(7 downto 0);
signal sfrdataports : STD_LOGIC_VECTOR(7 downto 0);
signal int_p0o : STD_LOGIC_VECTOR(7 downto 0);
signal int_p1o : STD_LOGIC_VECTOR(7 downto 0);
signal int_p2o : STD_LOGIC_VECTOR(7 downto 0);
signal int_p3o : STD_LOGIC_VECTOR(7 downto 0);
-----------------------------------------------------------------
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