system.mhs

xapp from xilinx very hard to find and very usefull application note from the great firm from USA

# ########################################################################
# Copyright(C) 2007 by Xilinx, Inc. All rights reserved.                ##
# 									##
# You may copy and modify these files for your own internal use solely  ##
# with Xilinx programmable logic devices and  Xilinx EDK system or      ##
# create IP modules solely for Xilinx programmable logic devices and    ##
# Xilinx EDK system. No rights are granted to distribute any files      ##
# unless they are distributed in Xilinx programmable logic devices.     ##
# 									##
# Source code is provided  as-is , with no obligation on the part of    ##
# Xilinx to provide support.                                            ##
# 									##
# ########################################################################
# ########################################################################
# Memec Design Spartan-3 3S1500MB MCH OPB EMC Reference System for   	##
# Xilinx EDK 9.1i Service Pack 1 and ISE 9.1i Service Pack 3            ##
# Target Board:  Memec Design Spartan-3 3S1500MB with P160 Comm Module 2##
# Family:	 spartan3						##
# Device:	 XC3S1500						##
# Package:	 FG676							##
# Speed Grade:	 -4							##
# Processor: Microblaze							##
# System clock frequency: 66.000000 MHz					##
# Debug interface: On-Chip HW Debug Module				##
# On Chip Memory :  16 KB						##
# Total Off Chip Memory :   5 MB					##
# - SRAM_256Kx32 =   1 MB						##
# - FLASH2Mx32 =   4 MB							##
# ########################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_sin_pin = fpga_0_RS232_sin, DIR = I
 PORT fpga_0_RS232_sout_pin = fpga_0_RS232_sout, DIR = O
 PORT fpga_0_LEDs_4Bit_GPIO_d_out_pin = fpga_0_LEDs_4Bit_GPIO_d_out, DIR = O, VEC = [0:3]
 PORT fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A, DIR = O, VEC = [9:29]
 PORT fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_BEN_pin = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_BEN, DIR = O, VEC = [0:3]
 PORT fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_CEN_pin = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_CEN, DIR = O, VEC = [0:0]
 PORT fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_OEN_pin = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_OEN, DIR = O, VEC = [0:0]
 PORT fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_WEN_pin = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_WEN, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK
 PORT sys_rst_pin = sys_rst_s, DIR = I


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 6.00.b
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_AREA_OPTIMIZED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 8192
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 8192
 PARAMETER C_ICACHE_USE_FSL = 1
 PARAMETER C_DCACHE_USE_FSL = 1
 PARAMETER C_ICACHE_BASEADDR = 0x30000000
 PARAMETER C_ICACHE_HIGHADDR = 0x3000ffff
 PARAMETER C_ADDR_TAG_BITS = 2
 PARAMETER C_DCACHE_BASEADDR = 0x30000000
 PARAMETER C_DCACHE_HIGHADDR = 0x3000ffff
 PARAMETER C_DCACHE_ADDR_TAG = 2
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
# Microblaze caches connect to the MCH interfaces on the MCH OPB EMC
 BUS_INTERFACE IXCL = ixcl
 BUS_INTERFACE DXCL = dxcl
 PORT CLK = sys_clk_s
 PORT RESET = microblaze_rst
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
 PORT Interrupt = Interrupt
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_NUM_BUS_RST = 3
 PARAMETER C_NUM_PERP_RST = 11
 PORT Dcm_locked = dcm_0_lock
 PORT Aux_Reset_In = net_gnd
 PORT Slowest_sync_clk = sys_clk_s
 PORT Chip_Reset_Req = net_gnd
 PORT Ext_Reset_In = sys_rst_s
 PORT Bus_Struct_Reset = bus_rst_0 & bus_rst_1 & bus_rst_2
 PORT Peripheral_Reset = periph_rst_0 & periph_rst_1 & periph_rst_2 & periph_rst_3 & periph_rst_4 & periph_rst_5 & periph_rst_6 & periph_rst_7  & periph_rst_8 & periph_rst_9 & periph_rst_10
 PORT Core_Reset_Req = Debug_Rst
 PORT System_Reset_Req = Debug_SYS_Rst
 PORT Rstc405resetcore = microblaze_rst
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT OPB_Rst = periph_rst_0
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
 PORT Debug_SYS_Rst = Debug_SYS_Rst
 PORT Debug_Rst = Debug_Rst
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = bus_rst_0
 PORT OPB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = bus_rst_1
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = bus_rst_2
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
 PORT LMB_Rst = periph_rst_1
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
 PORT LMB_Rst = periph_rst_2
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
 PORT BRAM_Rst_A = periph_rst_3
 PORT BRAM_Rst_B = periph_rst_4
END

BEGIN opb_uart16550
 PARAMETER INSTANCE = RS232
 PARAMETER HW_VER = 1.00.d
 PARAMETER C_IS_A_16550 = 1
 PARAMETER C_BASEADDR = 0x40400000
 PARAMETER C_HIGHADDR = 0x4040ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT OPB_Rst = periph_rst_5
 PORT IP2INTC_Irpt = RS232_IP2INTC_Irpt
 PORT sin = fpga_0_RS232_sin
 PORT sout = fpga_0_RS232_sout
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT OPB_Rst = periph_rst_6
 PORT GPIO_d_out = fpga_0_LEDs_4Bit_GPIO_d_out
END

BEGIN mch_opb_emc
 PARAMETER INSTANCE = P160_SRAM_256Kx32_FLASH_1Mx32
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_MCH_OPB_CLK_PERIOD_PS = 15151
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_NUM_CHANNELS = 2
 PARAMETER C_INCLUDE_OPB_IPIF = 1
 PARAMETER C_INCLUDE_OPB_BURST_SUPPORT = 1
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_TCEDV_PS_MEM_0 = 60000
 PARAMETER C_TWC_PS_MEM_0 = 60000
 PARAMETER C_TAVDV_PS_MEM_0 = 60000
 PARAMETER C_TWP_PS_MEM_0 = 60000
 PARAMETER C_THZCE_PS_MEM_0 = 10000
 PARAMETER C_TLZWE_PS_MEM_0 = 10000
 PARAMETER C_MEM0_BASEADDR = 0x30000000
 PARAMETER C_MEM0_HIGHADDR = 0x300fffff
 PARAMETER C_MEM1_BASEADDR = 0x30100000
 PARAMETER C_MEM1_HIGHADDR = 0x301fffff
 PARAMETER C_MEM2_BASEADDR = 0x30200000
 PARAMETER C_MEM2_HIGHADDR = 0x302fffff
 PARAMETER C_MEM3_BASEADDR = 0x30300000
 PARAMETER C_MEM3_HIGHADDR = 0x303fffff
 PARAMETER C_SYNCH_PIPEDELAY_0 = 2
# ICACHE
 PARAMETER C_MCH0_ACCESSBUF_DEPTH = 16
 PARAMETER C_MCH0_RDDATABUF_DEPTH = 0
 PARAMETER C_XCL0_LINESIZE = 4
 PARAMETER C_XCL0_WRITEXFER = 0
# DCACHE
 PARAMETER C_MCH1_ACCESSBUF_DEPTH = 16
 PARAMETER C_MCH1_RDDATABUF_DEPTH = 0
 PARAMETER C_XCL1_LINESIZE = 4
 PARAMETER C_XCL1_WRITEXFER = 1
 BUS_INTERFACE SOPB = mb_opb
# MCH Interfaces connect to the Microblaze Caches
 BUS_INTERFACE MCH0 = ixcl
 BUS_INTERFACE MCH1 = dxcl
 PORT MCH_OPB_Clk = sys_clk_s
 PORT MCH_OPB_Rst = periph_rst_7
 PORT Mem_A = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_split
 PORT Mem_DQ = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ
 PORT Mem_BEN = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_BEN
 PORT Mem_WEN = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_WEN
 PORT Mem_OEN = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_OEN
 PORT Mem_CEN = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_CEN
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Rst = periph_rst_8
 PORT Irq = Interrupt
 PORT Intr = RS232_IP2INTC_Irpt & DMA_Irpt
END

BEGIN util_bus_split
 PARAMETER INSTANCE = P160_SRAM_256Kx32_FLASH_1Mx32_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 9
 PARAMETER C_SPLIT = 30
 PORT Sig = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_split
 PORT Out1 = fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLKDV_BUF = TRUE
 PARAMETER C_CLKDV_DIVIDE = 1.500000
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLKDV = sys_clk_s
 PORT CLK0 = dcm_0_FB
 PORT CLKFB = dcm_0_FB
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN opb_central_dma
 PARAMETER INSTANCE = opb_central_dma_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41e00000
 PARAMETER C_HIGHADDR = 0x41e0ffff
 PARAMETER C_READ_OPTIONAL_REGS = 1
 BUS_INTERFACE SOPB = mb_opb
 BUS_INTERFACE MOPB = mb_opb
 PORT SOPB_Clk = sys_clk_s
 PORT MOPB_Clk = sys_clk_s
 PORT SOPB_Rst = periph_rst_9
 PORT MOPB_Rst = periph_rst_10 
 PORT DMA_Interrupt = DMA_Irpt
END