system.ucf

xapp from xilinx very hard to find and very usefull application note from the great firm from USA

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##  Copyright(C) 2007 by Xilinx, Inc. All rights reserved.               ##
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##  You may copy and modify these files for your own internal use solely ##
##  with Xilinx programmable logic devices and  Xilinx EDK system or     ##
##  create IP modules solely for Xilinx programmable logic devices and   ##
##  Xilinx EDK system. No rights are granted to distribute any files     ##
##  unless they are distributed in Xilinx programmable logic devices.    ##
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##  Source code is provided "as-is", with no obligation on the part of   ##
##  Xilinx to provide support.                                           ##
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# Target Board:  Memec Design Spartan-3 3S1500MB with P160 Comm Module 2 Rev 2
# Family:	 spartan3
# Device:	 XC3S1500
# Package:	 FG676
# Speed Grade:	 -4
###########################################################################

Net sys_clk_pin LOC=A13 | IOSTANDARD = LVCMOS33 ;
Net sys_rst_pin LOC = AC25  | IOSTANDARD = LVCMOS33 | PULLUP;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;

##Net sys_rst_pin TIG;

## FPGA pin constraints
Net fpga_0_RS232_sin_pin LOC = A3  | IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_sout_pin LOC = B4  | IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<0> LOC = W7 | IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<1> LOC = R7 | IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<2> LOC = R6 | IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<3> LOC = U6 | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<29> LOC = C12   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<28> LOC = G9    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<27> LOC = E10   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<26> LOC = C13   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<25> LOC = F7    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<24> LOC = F11   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<23> LOC = F12   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<22> LOC = G12   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<21> LOC = K3    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<20> LOC = J3    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<19> LOC = B3    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<18> LOC = L4    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<17> LOC = J4    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<16> LOC = H3    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<15> LOC = M1    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<14> LOC = N1    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<13> LOC = C4    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<12> LOC = E12   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<11> LOC = D13   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<10> LOC = K4    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_A_pin<9> LOC = E13   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<31> LOC = G2    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<30> LOC = F6    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<29> LOC = G1    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<28> LOC = D5    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<27> LOC = K2    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<26> LOC = J2    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<25> LOC = M2    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<24> LOC = L2    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<23> LOC = D6    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<22> LOC = H2    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<21> LOC = C6    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<20> LOC = H1    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<19> LOC = K1    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<18> LOC = E5    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<17> LOC = C5    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<16> LOC = L1    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<15> LOC = E11   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<14> LOC = E6    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<13> LOC = D11   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<12> LOC = G11   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<11> LOC = C10   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<10> LOC = G10   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<9> LOC = E7    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<8> LOC = A7    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<7> LOC = E4    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<6> LOC = F5    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<5> LOC = H13   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<4> LOC = H12   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<3> LOC = F10   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<2> LOC = H11   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<1> LOC = D10   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_DQ_pin<0> LOC = F9    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_BEN_pin<3> LOC = P2    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_BEN_pin<2> LOC = P1    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_BEN_pin<1> LOC = R3    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_BEN_pin<0> LOC = P4    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_WEN_pin LOC = G13   | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_OEN_pin<0> LOC = D1    | IOSTANDARD = LVCMOS33;
Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_CEN_pin<0> LOC = D2    | IOSTANDARD = LVCMOS33;

# Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_OEN_pin<1> LOC = N2    | IOSTANDARD = LVCMOS33;
# Net fpga_0_P160_SRAM_256Kx32_FLASH_1Mx32_Mem_CEN_pin<1> LOC = D7    | IOSTANDARD = LVCMOS33;