rs_enc.v

Verilog code for RS-(255,239) encoder.

//--------------------------------------------------------------------//
//                  Generated by RSTK                                 //
//                      rs_enc.v                                      //
//                                                                    //
//--------------------------------------------------------------------//

module rs_enc 
(
    rst_n,
    clk,
    in_valid,
    in_data,
    in_start,
    in_end,
    in_ready,
    out_valid,
    out_data,
    out_start,
    out_end,
    out_ready,
    out_synv,
	 out_trig//added
);

// module parameters
parameter N = 255;  // Total number of encoder output symbols
parameter K = 239;  // Number of encoder input symbols

// module interface signals
input         rst_n;
input         clk;
input         in_valid;
input  [7:0]  in_data;
input         in_start;
input         in_end;
output        in_ready;
output        out_valid;
output [7:0]  out_data;
output        out_start;
output        out_end;
input         out_ready;
output        out_synv;
output        out_trig;//added

`include "G:\projectsoft\work\m1\rtl\gf_arith.v"

// locals
reg out_synv;
reg [7:0] din_r;
wire [7:0] g0, g1, g2, g3, g4, g5, g6, g7;
wire [7:0] g8, g9, g10, g11, g12, g13, g14, g15;
reg [7:0] g0_r, g1_r, g2_r, g3_r, g4_r, g5_r, g6_r, g7_r;
reg [7:0] g8_r, g9_r, g10_r, g11_r, g12_r, g13_r, g14_r, g15_r;
wire [7:0] g16;
wire [7:0] feedback;
reg [7:0] xfer_cnt;
reg done, enb_enc, enc_feedback, syn_valid;
reg [1:0] RSENC_SM;
reg end_r, valid_r, start_r, int_ready;

// constants
`define RS_ENC_S0   2'd0
`define RS_ENC_S1   2'd1
`define RS_ENC_S2   2'd2
`define RS_ENC_S3   2'd3

assign in_ready = out_ready && int_ready;

// calculate check symbols
assign g0 = gfmul_136(feedback);
assign g1 = gfmul_75(feedback);
assign g2 = gfmul_99(feedback);
assign g3 = gfmul_196(feedback);
assign g4 = gfmul_86(feedback);
assign g5 = gfmul_42(feedback);
assign g6 = gfmul_198(feedback);
assign g7 = gfmul_204(feedback);
assign g8 = gfmul_57(feedback);
assign g9 = gfmul_187(feedback);
assign g10 = gfmul_164(feedback);
assign g11 = gfmul_246(feedback);
assign g12 = gfmul_18(feedback);
assign g13 = gfmul_111(feedback);
assign g14 = gfmul_252(feedback);
assign g15 = gfmul_211(feedback);
assign g16 = g15_r;
assign feedback = (enc_feedback) ? (g16 ^ din_r) : 8'b0;
assign out_data = (enc_feedback) ? din_r : g16;

always @ (negedge rst_n or posedge clk)
begin 
    if (!rst_n) 
        din_r <= 0;
    else if (in_valid)
        din_r <= in_data;
end 

always @ (negedge rst_n or posedge clk)
begin 
    if (!rst_n) 
    begin
        g0_r <= 0;
        g1_r <= 0;
        g2_r <= 0;
        g3_r <= 0;
        g4_r <= 0;
        g5_r <= 0;
        g6_r <= 0;
        g7_r <= 0;
        g8_r <= 0;
        g9_r <= 0;
        g10_r <= 0;
        g11_r <= 0;
        g12_r <= 0;
        g13_r <= 0;
        g14_r <= 0;
        g15_r <= 0;

    end
    else if (in_start && in_valid)
    begin
        g0_r <= 0;
        g1_r <= 0;
        g2_r <= 0;
        g3_r <= 0;
        g4_r <= 0;
        g5_r <= 0;
        g6_r <= 0;
        g7_r <= 0;
        g8_r <= 0;
        g9_r <= 0;
        g10_r <= 0;
        g11_r <= 0;
        g12_r <= 0;
        g13_r <= 0;
        g14_r <= 0;
        g15_r <= 0;
    end
    else if (out_valid)
    begin
        g0_r <= g0;
        g1_r <= g0_r ^ g1;
        g2_r <= g1_r ^ g2;
        g3_r <= g2_r ^ g3;
        g4_r <= g3_r ^ g4;
        g5_r <= g4_r ^ g5;
        g6_r <= g5_r ^ g6;
        g7_r <= g6_r ^ g7;
        g8_r <= g7_r ^ g8;
        g9_r <= g8_r ^ g9;
        g10_r <= g9_r ^ g10;
        g11_r <= g10_r ^ g11;
        g12_r <= g11_r ^ g12;
        g13_r <= g12_r ^ g13;
        g14_r <= g13_r ^ g14;
        g15_r <= g14_r ^ g15;
    end 
end

always @ (negedge rst_n or posedge clk)
begin 
    if (!rst_n) 
    begin
        RSENC_SM <= `RS_ENC_S0;
        xfer_cnt <= 0;
        enc_feedback <= 1'b0;
        enb_enc <= 1'b0;
        int_ready <= 1'b0;
    end
    else
    begin
        case (RSENC_SM)
            `RS_ENC_S0: 
            begin
                if (in_start && in_valid)
                begin
                    RSENC_SM <= `RS_ENC_S1;
                    enb_enc <= 1'b1;
                    enc_feedback <= 1'b1;
                end
                else
                    RSENC_SM <= `RS_ENC_S0;

                int_ready <= 1'b1;
            end

            `RS_ENC_S1:
            begin
                if (((xfer_cnt == (K-1)) || end_r) && out_ready) 
                begin
                    RSENC_SM <= `RS_ENC_S2;
                    xfer_cnt <= 0;
                    enc_feedback <= 1'b0;
                end
                else if (in_valid) 
                    xfer_cnt <= xfer_cnt + 1;

                if (in_valid && (in_end || (xfer_cnt == K-2)))
                    int_ready <= 1'b0;
            end

            `RS_ENC_S2:
                if (out_ready)
                begin
                    if (xfer_cnt == (N-K-1))
                    begin
                        RSENC_SM <= `RS_ENC_S0;
                        enb_enc <= 1'b0;
                        xfer_cnt <= 0;
                        int_ready <= 1'b1;
                    end
                    else
                        xfer_cnt <= xfer_cnt + 1;
                end

            default:
                RSENC_SM <= `RS_ENC_S0;
        endcase
    end
end

assign out_valid = enb_enc & (((RSENC_SM != `RS_ENC_S2) & valid_r) | ((RSENC_SM == `RS_ENC_S2) && out_ready));

always @ (negedge rst_n or posedge clk)
begin 
    if (!rst_n) 
    begin 
        end_r <= 1'b0;
        valid_r <= 1'b0;
        start_r <= 1'b0;
    end 
    else 
    begin 
        if (!end_r && in_valid && in_end)
            end_r <= 1'b1;
        else if (end_r && out_ready)
            end_r <= 1'b0;

        valid_r <= in_valid;
        start_r <= in_start;
    end 
end 

always @ (negedge rst_n or posedge clk)
begin 
    if (!rst_n)
        syn_valid <= 1'b0;
    else if ((RSENC_SM == `RS_ENC_S1) && in_valid && (in_end || (xfer_cnt == K)))
        syn_valid <= 1'b1;
    else if (done)
        syn_valid <= 1'b0;
end

always @ (negedge rst_n or posedge clk)
begin 
    if (!rst_n)
        out_synv <= 1'b0;
    else if (!out_synv && syn_valid && out_ready)
        out_synv <= 1'b1;
    else if (out_synv && done)
        out_synv <= 1'b0;
end

always @ (negedge rst_n or posedge clk)
begin 
    if (!rst_n)
        done <= 1'b0;
    else if ((RSENC_SM == `RS_ENC_S2) && (xfer_cnt == (N-K-2)) && out_ready)
        done <= 1'b1;
    else if (out_ready)
        done <= 1'b0;
end

assign out_end = done;
assign out_start = out_valid & start_r;
assign out_trig = out_synv & clk;
endmodule